Enhancing cache coherence protocols with emerging interconnect technologies

Subject
Since few years we are witnessing the emergence of manycore architectures, namely to the implementation of massive parallelism on a single chip. Associated with the shrinking size of the transistors, these manycore architectures should reach the integration of thousands of heterogeneous cores allowing huge parallel computation capabilities suitable for high-performance embedded computing systems and HPC. 
These parallelism capabilities obviously generate an enormous amount of data exchanges making the communication medium a key element of the overall performance of the system. However, because of the difference of speed between the processors and the main memory, fast and small dedicated hardware-controlled memories containing copies of parts of the main memory (a.k.a caches) are used [1]. To keep these distributed copies up-to-date and synchronize the accesses to shared data, it requires to share information between some may if not all the nodes. This leads to increase the number of data transfers that must be supported by the interconnection media. Furthermore, these specific data transfers concern generally one source and several destinations, which correspond to multicast/broadcast communications.
In parallel, technology evolution has allowed for the integration of silicon photonics and wireless communications on chip, thus leading to the Wireless Network-on-Chip (WiNoC) [2-3] and Optical Network-on-Chip (ONoC) [4-5] paradigms. These emerging technologies are showing significant advantages for broadcasting data (WiNoC) and low-latency communications (ONoC), whereas conventional Electrical Network-on-Chip (ENoC) is reaching its limit [6]. For future on-chip interconnect, it seems clear that the use of just one technology will lead to inefficient solutions. However, relying on the best technology choice for each type of data transfers is a key to support the quality of service needed at application and system levels.
In this context, the main objective of this project is to explore how combining these emerging technologies can improve the efficiency of on-chip interconnection systems of shared-memory manycore architectures based on cache coherence protocols. We will study new cache protocols which are well adapted for the specific properties of hybrid interconnects.  Model of communications for each media/technology will be defined, in terms of data transfer latency, power consumption, etc., and these models will be used at the operating system level to select the best media for each type of transfer. For that, on-line mechanisms will be developed to evaluate the network traffics, and to estimate the optimal path for each new communication.

The scope of the PostDoc position is relatively open and applicants are expected to identify the direction that suits them the most as a function of their background and interest. The goal is to improve performance and energy efficiency of on-chip interconnect in the context of manycore architectures, and we seek to find systematic methods to answer the key questions:
•    How emerging interconnect can influence the classic cache coherency protocols?
•    Can efficient broadcast offered by WiNoC and low-latency of ONoC be leveraged to improve on-chip interconnect performance?
•    Can we provide new cache coherency protocols taking advantage of emerging interconnect technologies?

Bibliography

[1]    M. MK Martin, M. D. Hill, and D. J. Sorin. "Why on-chip cache coherence is here to stay." Communications of the ACM 55.7 (2012): 78-89.
[2]    A. Karkar et al. “A Survey of Emerging Interconnects for On-Chip Efficient Multicast and Broadcast in Many- Cores”. In: IEEE Circuits and Systems Magazine 16., pp. 58–72 , 2016.
[3]    M. F. Chang, et al., “CMP Network-on-Chip Overlaid with Multi-Band RF-Interconnect,” Proc. of IEEE Int. symposium on High- Performance Computer Architecture (HPCA), pp. 191-202, 2008.
[4]    A. Shacham, K. Bergman, and L. P. Carloni. "Photonic networks-on-chip for future generations of chip multiprocessors." IEEE Transactions on Computers, vol. 57.9 pp: 1246-1260, 2008.
[5]    J.  Ortiz Sosa, O. Sentieys, C. Roland. A Diversity Scheme to Enhance the Reliability of Wireless NoC in Multipath Channel Environment. Twelfth IEEE/ACM International Symposium on Networks-on-Chip (NOCS), Oct 2018, Torino, Italy. pp.1-8
[6]    J. Luo, C. Killian, D. Chillet, S. Le Beux, I. OConnor, O. Sentieys. “Offline optimization of wavelength allocation and laser power in nanophotonic interconnects”. In: ACM Journal on Emerging Technologies in Computing Systems (JETC) (2018).