Time-Aware Reliability Enhancements for Safety-Critical Embedded Systems

Embedded systems are increasingly vulnerable to radiation due to the use of tiny transistors, low voltages, and high frequencies, etc. Common fault tolerance approaches, such as Triple Modular Redundancy (TMR), incur area overhead. Most Worst-Case Execution Time (WCET) estimations required for timing guarantees are faults-free or only mitigate memory faults, and the processing units are assumed fault-free, which is unsafe when faults occur. Task replication increases timing overheads, leading to over-dimensioning. To address these limitations, this thesis enhances vulnerability analysis with functional and timing correctness of systems under faults, showing the impact of faults on WCET estimations, using a RISC-V processor based on High-Level Synthesis (HLS). Furthermore, it proposes low-complexity, low-overhead dual-core locksteps for fault tolerance, with fast error detection and rollback mechanisms that incur near-zero timing overhead to recover the correct processor state. The analysis is further enhanced to assess the impact of compiler optimizations on reliability across multiple inputs and varying application optimization levels, and to propose selective instruction-level replication.