Real-time and reliable design for safety-critical embedded systems

Type de soutenance
Date de début
Date de fin
IRISA Rennes
Salle Métivier
Angeliki KRITIKAKOU - Equipe TARAN
Département principal

Vous êtes cordialement invités à venir assister à la soutenance d'HDR d'Angeliki KRITIKAKOU, équipe TARAN, le lundi 28 novembre 2022 à 10h00 en salle Métivier.

Real-time and reliable design for safety-critical embedded systems

Embedded systems in safety-critical domains, such as avionics, space, automotive, health-care, require hard real-time and reliable application execution. As applications are becoming more complex, their computational demands scale rapidly. To address these demands, architectures with multiple processing elements are required, able to concurrently execute a high volume of applications. However, the increased complexity combined with novel transistor technologies have introduced reliability and real-time issues to modern embedded systems.

Reliable execution is under threat due to the increased fault susceptibility of modern electronic systems, such as manufacturing process variation, aging and soft errors. Typical reliability solutions, that rely on full redundancy, usually entail significant cost, latency and resource overheads, which are often not suitable for safety-critical embedded systems. To cost-effectively address these reliability threats, the system must be properly analysed and enhanced with effective fault tolerance means. Furthermore, to provide hard real-time guarantees, the Worst-Case Execution Time (WCET) estimations have to be considered during system analysis and design. However, WCET are overestimated due to application and hardware complexity. As a result, system deployment approaches lead to solutions that over-allocate the resources to critical applications, degrading system performance.

During this defence, I will highlight the challenges related to the design of real-time and reliable safety-critical embedded systems and summarize the contributions in this domain. Then, we will discuss in more details our cross-layer realistic reliability analysis for complex hardware designs under transient faults and our safe run-time mechanisms to improve system performance providing real-time guarantees. Last, we will conclude with several research openings for future directions.

Composition du jury
- Alberto BOSIO, Professor, École Centrale de Lyon, Rapporteur
- Lirida Alves DE BARROS NAVINER, Professor, Telecom ParisTech, Rapporteur
- Jari NURMI, Professor, Tampere University, Finland, Rapporteur
- Smail NIAR, Professor, Université Polytechnique Hauts-de-France, Examiner
- Olivier SENTIEYS Professor, University of Rennes 1, France, Examiner
- Dimitrios SOUDRIS, Professor, National Technical University of Athens, Greece, Examiner