Even in the multicore era, making single cores faster is paramount to achieve high-performance computing, given the existence of programs that are either inherently sequential or expose nonnegligible sequential parts. Sequential performance has been essentially improving with the scaling of the processor structures that enable instruction-level parallelism (ILP). However, as modern microarchitectures continue to extract more ILP by employing larger instruction windows, true data dependencies remain a major performance bottleneck. Value Prediction (VP) and Load-Address Prediction (LAP) are two developing techniques that allow to overcome this obstacle and harvest more ILP by enabling the execution of instructions in a data-wise speculative manner.
This thesis proposes mechanisms that are related with VP and LAP and lead to effectively higher performance improvements. First, VP is examined in an ISA-aware manner, that discloses the impact of certain ISA particularities on the anticipated speedup. Second, a novel binary-based VP model is introduced, namely VSEP, that allows to exploit certain value patterns that although they are encountered frequently, they cannot be captured by previous works. VSEP improves the obtained speedup by 19% and also, by virtue of its structure, it mitigates the cost of predicting values wider than 64 bits. By adapting this approach to perform LAP allows to predict the memory addresses of 48% of the committed loads. Eventually, a microarchitecture that leverages this LAP mechanism can execute 32% of the committed loads early.
Smail Niar, Professeur, Université Polytechnique Hauts-de-France, Valenciennes
Sébastien Pillement, Professeur, Université de Nantes
Alain Ketterlin, Maître de conférence, Université Louis Pasteur, Strasbourg
Angeliki Kritikakou, Maître de conférence, Université de Rennes 1
André Seznec, Directeur de recherche, Inria Rennes