OBESSA: efficient designs of On-Board heterogeneous Embedded Systems for Space Applications

Thesis Context

Due to increased system requirements and power dissipation issues of single-core systems, the chip market has moved towards Multiprocessor System-on-Chip (MPSoC) architectures [1]. MPSoC architectures consist of several processing elements, which together can offer a massive computing power, enabling higher embedded processing capacities. Furthermore, programmable processors have been extended with specialized hardware accelerators [2], leading to heterogeneous MPSoC, which combine both software (SW) and hardware (HW) computational resources for a more efficient utilization.

In the space industry, ground applications are typically executed on general purpose systems, exploiting parallelism and high performance offered by several system cores. For instance, several signal processing and imaging applications are based on Fourier transforms; e.g., a "hand-coded" Fourier transform is used for source localization in MXT software, an external high-performance FFTW library is used for repeated and frequent deconvolutions of the detector images in ECLAIRs and other libraries are used for adjustments, e.g., in GSL. Within the edge computing paradigm, part of the centralized processing is being moved to the devices generating data at the edge of the network, in order to save bandwidth and reduce response latencies due to communications, while helping to protect privacy [3]. Similarly, the space industry can take advantage of the latest hardware architecture evolutions in embedded systems, in order to migrate the data processing, typically occurring at the ground base station, to on-board processing [4]. In this way, the system autonomy will be increased, and monitoring and detection latency, alongside with downlink throughput, will be significantly reduced. Hence, the overall system performance and energy consumption can be improved. Such on-board mitigation can be achieved if key compute-intensive algorithms for current and upcoming space applications are efficiently mapped on heterogeneous embedded MPSoC architectures, guaranteeing a certain level of performance and robustness for space missions.

However, design and programming such high-performance heterogeneous embedded MPSoC architectures, combining multiple processor cores and hardware accelerators, is a real challenge [5]. Performance, energy consumption and quality of service depend on a large set of parameters, regarding both the mathematical algorithms, alongside with their use scenario, and the MPSoC design. For instance, the size of the input data affects the processing requirements of an FFT, whereas the HW/SW partitioning, the type of HW implementation and the communication cost affect the quality of the final system design. Design Space Exploration (DSE) methodologies are required to efficiently explore the space of design options in order to find the best architectural trade-offs and mappings of the application on the targeted architecture.

Thesis Goal
The goal of this PhD thesis is to propose a design space exploration method that targets heterogeneous MPSoC architectures for high performance on-board processing, based on identified key algorithms required in current and future space systems. Our approach to reach this goal can be decomposed in the following four tasks:
T1: identify key algorithms and scientific/mathematical computations required for current and future onboard processing requirements in the space domain
T2: characterize them to understand the performance bottlenecks and identify potential acceleration options, targeting cutting-edge heterogeneous, high performance embedded computing platforms
T3: devise processing architectures that enable efficient HW/SW mappings to accelerate the algorithms and a design space exploration methodology
T4: prototype and characterize implementations of the proposed architectures that exploit the architectural advancements available in selected heterogeneous processing platforms for high performance on-board processing required in current and future space systems.

Detailed Description
Task 1 identifies the use case requirements. It is the input to this PhD thesis, the domain of knowledge that defines the functional and non-functional application requirements as identified by the leading actors in the field. From the analysis of these requirements, this task will identify and rank a set of metrics, or Key Performance Indicators (KPIs), that will help evaluate the system and which might include execution time, area, power consumption, energy efficiency and quality of results. To achieve this goal, we will initially interview space scientific institutes and space actors (such as IAS, IRAP, LAM, LPC2E, CEA, ESA, etc.) in order to identify a set of key processing algorithms (mathematical operations, scientific computations), required by existing and potentially future space missions that are amenable to be moved from ground level to on-board processing, as well as the mentioned metrics for the system evaluation.

Task 2 will characterize the identified key algorithms to understand the performance bottlenecks and feed the hardware design process. We will characterize the workloads resulting from the execution of the algorithms and identify the computational requirements demanded. This information will offer hints on the required heterogeneous MPSoC architecture required, the type of CPU cores, the accelerators suitable for the analyzed workloads and the memory architecture, which might be one of the factors with the highest impact on the final performance. For each identified key algorithm, various design knobs covering different performance-power-cost trade-offs will be explored and characterized, for both HW and SW targets.

Task 3 tackles the design of the MPSoC architecture able to satisfy the identified computational demands. We plan to leverage on heterogeneous, high performance embedded computing platforms, like Xilinx Ultrascale+ MPSoCs [6] and Versal [7], and on European technology available in high-end, radiation-hardened devices such as NanoXplore NG-ULTRA [8]. This will allow us to explore different HW/SW partitioning alternatives enabled by the latest architectural innovations. Generally speaking, the mentioned platforms are composed of different combinations of: (i) ARM Cortex-A and/or Cortex-R cores; (ii) Programmable Logic and DSP blocks for custom hardware accelerators; (iii) reconfigurable memory hierarchy; and (iv) GPU and AI engines in the Versal family, composed of tiles of vector processors suitable for AI/ML and signal processing computations. We will hence explore, as dictated by the computations dataflow, the use of loosely and tightly coupled accelerators attached to the ARM complex and/or to a RISC-V [9] in the FPGA part of the SoC, as well as mappings onto other domain-specific accelerators available, like the vector processors in the AI engines in Versal. Informed by the characterization done in Task 2, we will pay special attention to the design of the memory architecture, exploiting the fact that the described platforms offer a reconfigurable memory hierarchy that can be adapted to the application demands. In this memory architecture, it will be very important to define efficient data layouts that optimize the use of the available communication resources to maximize bandwidth.

Task 4 deals with building prototype implementations of the devised architectures in Task 3 and characterizing the obtained performance in the selected processing platforms. These platforms (NG-ULTRA, Xilinx Ultrascale+/Versal) will be selected according to their degree of adaptation to the computational requirements and to strategic decisions agreed with the involved partners from the space scientific institutes. As an output of this task, and hence of the thesis, we expect to have a set of architectural constructs that fits the needs of future on-board processing systems in space applications and its characterization using the selected platforms. We will propose DSE methodologies to explore the space of heterogeneous MPSoC architectures and implementations, in order to identify promising architectural solutions based on the agreed metrics (or KPIs). Hence, as a result of this DSE we could be able to offer recommendations on which architectures are better suited to which platforms in order to satisfy the above-mentioned metrics when defining upcoming space missions requirements.