Fault tolerant emerging on-chip interconnects for manycore architectures

Subject

Since few years we are witnessing the emergence of manycore architectures, namely to the implementation of massive parallelism on a single chip. Associated with the shrinking size of the transistors, announced reaching an 11nm technology on 2020, these manycore architectures should reach the integration of thousands of heterogeneous cores allowing huge parallel computation capabilities suitable for High Performance Computing (HPC) and embedded systems.

These parallelism capabilities obviously generate an enormous amount of data exchanges making the communication medium a key element of the overall performance of the system. Massively parallel manycore architectures are showing the scalability limits of electrical NoCs (ENoCs) that suffer when facing thousands of cores. This generates an increase in the latency, hence in the power consumption. Theses degradations are also amplified while the size of the wire decreases.

Technology evolution has allowed for the integration of silicon photonics and wireless on- chip communications, creating Optical and Wireless NoCs (ONoCs and WNoCs, respectively) paradigms. The recent publications highlight advantages for each technology: WNoCs are efficient for broadcast, ONoCs have low latency, while ENoC still efficient for average size of NoC. In this context, on-chip interconnects mixing these technologies are good candidates for future manycore architectures.

In WNoCs and ONoCs, the conversion between electric and wireless, or Optical, signals are done by using Network interfaces (NIs). Due to architectural constraints, these NIs are shared between several cores (e.g. 4 cores). Hence, if any NI undergoes an error and became faulty, the performance degradation within the manycore is critical. Indeed, given the shrinking size of the transistors and the process complexity of emerging technologies, the interconnects become more subject to defects. This leads to faults appearing at runtime, due to electronic perturbations or aging, or during the fabrication process. Thus, error detection and correction mechanisms or autonomic self-test must be integrated in today’s architectures. This statement is enforced with the way to associate the different technologies: the network interfaces are becoming the doors to access each communication medium, and any fault in these blocks will degrade the performance of the system. This performance degradation is mainly due to high traffic rerouting creating bottlenecks or cluster isolation.

The aim of this thesis is to integrate fault-tolerance mechanisms to ensure the overall performance of the NoC.

The main objectives of this thesis are:

• Defining techniques to use a faulty Network Interface (optical or wireless) in a degraded mode;
• Propose hardware techniques to improve the resilience of the NIs;
• While considering degraded NIs, provide adaptive Quality of Service by efficiently routing the messages on the most efficient technology with respect to an objective (e.g. minimizing energy, latency, etc.).

Main activities

The thesis works will be organized regarding the following activities:

• The first activity consists in the study of the state of the art in recent advances for each on-chip interconnect technology. This study will allow to identify fault models for the NIs.
• Techniques, like Error Correcting Codes, hardware or temporal redundancy, need to be apply to the NIs to enhance the reliability or to allow the use in a degraded mode.
• The third activity is the characterization of communication models (energy, throughput, latency) for each degraded NIs. The aim is to define high level models to integrate them in a manycore simulator (e.g. NoXiM, Sniper or Gem5) in order to evaluate communication performance degradation on real life benchmark.
• Regarding the last activity, we will propose routing protocols to provide a Quality of Service (QoS) to the application by targeting a minimal energy consumption, or latency. This routing protocol will define, regarding the targeted QoS and the message profile, the path among the hybrid interconnect and the degraded NIs.

The student will evolve in a very stimulating environment as 2 PhD students are currently working on ENoC and ONoC, and a PostDoC researcher is working on WNoCs.

This PhD work will also interact with other ANR projects: Rakes and AllOpticall2.  These projects involve Inria Cairn (Rennes/Lannion), INL (Lyon), Concordia University (Montreal, Canada), Lab-STICC (Lorient), TIMA (Grenoble), and C2N (Paris).

Profile of the candidates

• Master student in computer science;
• Knowledges and skills in
  • embedded digital architectures, parallel computing;
  • coding in SystemC, C++, Python, VHDL/HLS, Matlab;

Knowledge in on-chip interconnects, and in optical and wireless communications, fault tolerance is a plus but is not mandatory.

Contacts and application

• Daniel CHILLET, daniel [*] chilletirisa [*] fr (daniel[dot]chillet[at]irisa[dot]fr)
• Cédric KILLIAN, cedric [*] killianirisa [*] fr (cedric[dot]killian[at]irisa[dot]fr)

Please apply by sending an email (CV, cover letter, and Master results) to the aforementioned contacts with the following attachments:

• CV;
• Cover letter;
• Master results;
• Letters or reference person with contact’s information.