Séminaire SemSecuElec : Deux exposés

Séminaire
Date de début
Date de fin
Lieu
IRISA Rennes
Salle
Salle Pétri/Turing
Orateur
Paul Grandamme (Laboratoire Hubert Curien, Université Jean Monnet) - Antonio Ras (CEA-LETI)

Bonjour,

La prochaine session du séminaire sécurité des systèmes électroniques embarqués aura lieu le vendredi 25 Avril de 10h à 12h.
Le séminaire aura lieu dans les locaux de l'Inria Rennes, Salle Turing-Petri.

Le programme de cette session est le suivant : 

  • 10:00 - 11:00 - Paul Grandamme - Laboratoire Hubert Curien, Université Jean Monnet

    • Titre : Advanced techniques for fault injection attacks on integrated circuits

    • Résumé : The security of integrated circuits is evaluated through the implementation of attacks that exploit their inherent hardware vulnerabilities. Fault injection attacks represent a technique that is commonly employed for this purpose. These techniques permit an attacker to alter the nominal operation of the component in order to obtain confidential information.

Firstly, we propose the utilisation of the thermal effect of an infrared laser bench for the injection of permanent faults into the Flash memory of unpowered components. This novel attack vector gives rise to the delineation of a comprehensive new fault model, encompassing both the physical and application levels.

Secondly, we describe the use of unfocused X-ray sources for the injection of faults into the Flash memories of both powered and unpowered components. Furthermore, the thermal and temporal recovery phenomena are also characterised. The design and characterisation of masks that enable the focused injection of faults are demonstrated.

These novel attacks on unpowered devices, facilitated by fault injection using X-rays and lasers, necessitate a re-evaluation of the effectiveness of protection mechanisms against such attacks, particularly in regard to these novel attack vectors.

  • 11:00 - 12:00 - Antonio RAS - CEA-LETI

    • Titre : PHOENIX : the first crypto-agile hardware solution for ML-KEM and HQC

    • Résumé : The security of the public-key cryptography protecting today and tomorrow's communication is threatened by the advent of quantum computers. To address this challenge, post-quantum cryptography is employed to devise new quantum-resistant cryptosystems. The National Institute of Standards and Technology (NIST), which led the quantum-safe transition, has already standardized the first lattice KEM algorithm, called ML-KEM, and has recently selected HQC, a code-based KEM, as the second future standard. The relative immaturity of the current post-quantum cryptosystems encourages a crypto-agile approach, which maintains its security by adopting an easily transitions between schemes. Intelligent crypto-agility requires identifying and implementing efficient sharing strategies between operations, which is particularly challenging when considering cryptosystems belonging to different cryptographic families. Since the last HQC team update, polynomial multiplication has become the main bottleneck of the algorithm. An alternative state-of-the-art solution to replace this operation is the Frobenius Additive Fast Fourier Transform (FAFFT), an FFT-like operation applied in the binary field.

This talk presents PHOENIX, the first efficient crypto-agile hardware strategy for sharing polynomial multiplication operations in ML-KEM and HQC. Specifically, the two operations targeted by the mutualisation are the Number Theoretic Transform (NTT), for ML-KEM, and the Frobenius Additive FFT (FAFFT), for HQC. To achieve agility, PHOENIX uses a hardware design called SuperButterfly unit, which can be configured to perform all the processing elements, known as butterfly structure, contained in the selected multiplication operations.

To our knowledge, PHOENIX is the first sharing strategy proposal in lattice-code crypto-agility, and also the first existing FAFFT hardware accelerator. We demonstrate how PHOENIX can be efficiently integrated into ML-KEM and HQC at all three NIST security levels. We finally discuss the agility overhead, in terms of resource utilization, and the respective cryptosystems performance, for all the NIST security levels, using PHOENIX in a real system-on-chip FPGA scenario.

Le séminaire est ouvert à tous en présentiel et en distanciel.

Pour assister au séminaire en présentiel, l'inscription est obligatoire au moins 48h à l'avance pour tous les participants en présentiel auprès de Nadia Derouault nadia [*] derouaultatinria [*] fr (nadia[dot]derouault[at]inria[dot]fr) . Les participants externes devront se présenter à l'accueil avec une pièce d'identité.

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