Mitigating Spectre vulnerability in modern Out-of-Order Cores

In the continuous pursuit of faster computing, modern processors employ techniques to keep their resources as busy as possible. One such technique, speculative execution, predicts the outcome of instructions whose results are not yet available but are needed to determine the next steps of the program. This allows the processor to avoid being idle. However, it also introduced a flaw in the microarchitecture: mispredictions can be exploited to access sensitive data, giving rise to the Spectre vulnerability. The state-of-the-art offers various hardware and software protections. Hardware solutions are generally more comprehensive, but their real impact on performance remains debated due to differences in architecture and evaluation methodology. This thesis proposes a protection against Spectre on a RISC-V core. We first evaluate existing  protections, particularly selective speculation, an approach widely explored in both hardware and software. We assume that the microarchitecture cannot distinguish between secret and public data within a program. The results show that achieving perfect protection through selective speculation comes at a prohibitive performance cost. To overcome these limits, we propose a new solution that provides the microarchitecture with additional information about sensitive data.