Publications 2003

Academic Journals

1. A. Colin, I. Puaut, C. Rochange, P. Sainrat. Calcul de majorants de pire temps d'exécution : état de l'art. Techniques et Sciences Informatiques (TSI), 22(5):651-677, 2003.
2. A. Seznec, N. Sendrier. HAVEGE: a user-level software heuristic for generating empirically strong random numbers. ACM Transactions on Modeling and Computer Systems, October 2003.

International Conferences

1. A. Arnaud, I. Puaut. Towards a predictable and high performance use of instruction caches in hard real-time systems. In Proc. of the work-in-progress session of the 15th Euromicro Conference on Real-Time Systems, Pages 61-64, Porto, Portugal, July 2003.
2. M. Avila, M. Glaizot, I. Puaut. Impact of automatic gain time identification on tree-based static WCET analysis. In Proc. of the 3rd International Workshop on worst-case execution time analysis, in conjunction with the 15th Euromicro Conference on Real-Time Systems, Porto, Portugal, July 2003.
3. Assia Djabelkhir, André Seznec. Characterization of embedded applications for decoupled processor architecture. In Proceedings of the IEEE 6th Annual Workshop on Workload Characterization, Austin, TX, 2003.
4. Karine Heydemann, François Bodin, Peter Knijnenburg, Laurent Morin. UFC : a Global Tradeoff Strategy for Loop Unrolling for VLIW Architectures. In CPC'2003, Pages 59-70, 2003.
5. Karine Heydemann, Henri-Pierre Charles, François Bodin. Schéma de compression reconfigurable avec un émulateur logiciel pour la recherche de compromis entre la taille du code et sa performance. In RenPar'15/CFSE'3/SympAAA'2003, Pages 417-424, La Colle sur Loup, France, 2003.
6. Pierre Michaud. A statistical model of skewed-associativity. In Proceedings of the IEEE International Symposium on Performance Analysis of Systems and Software, Pages 204-213, March 2003.
7. André Seznec, Antony Fraboulet. Effective ahead pipelining of instruction block address generation. In Proceedings of the 30th Annual International Symposium on Computer Architecture (ISCA-03), Pages 241-252, 2003.

Research Reports

1. Amaury Darsch, André Seznec. Out-of-order execution of predicated instruction sets through translation register buffers. Research Report IRISA, No 1573, November 2003. download
2. Karine Heydemann, Henri-Pierre Charles, François Bodin. A compression scheme for code size versus performance trade-off. Research Report IRISA, No 1574, 2003.
3. Gilles Pokam, François Bodin. Energy reduction potential of a phase-based cache resizing scheme for embedded systems. Research Report IRISA, No 1582, December 2003. download
4. Gilles Pokam, François Bodin. Energy-Delay Tradeoff Analysis of ILP-based Compilation Techniques on a VLIW Architecture. Research Report IRISA, No 1572, November 2003. download
5. I. Puaut, A. Arnaud, D Decotigny. Performance analysis of static cache locking in multitasking hard real-time systems. Research Report IRISA, No 0, October 2003.
6. André Seznec. Redundant History Skewed Perceptron Predictors: pushing limits on global history branch predictors. Research report IRISA, No 1554, September 2003.

Thesis

1. Ronan Amicel. Simulation de jeux d'instructions ˆ hautes performances. PhD Thesis University of Rennes 1, January 2003.

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