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Applying formal methods to testing has recently become a quite popular research topic. In this paper we explore the opposite approach, namely, applying testing techniques to formal verification. The idea is to use test generation techniques to extract subsets (called components) from a specification and to perform the verification on the components rather than on the whole system. This may considerably reduce the verification effort and, under reasonable sufficient conditions, a safety property verified on a component also holds on the whole specification.
Vlad Rusu
Vlad.Rusu@irisa.fr
@InProceedings{rusu02a,
Author = {Rusu, V.},
Title = {Verification using test generation techniques},
BookTitle = {Formal Methods Europe (FME'02)},
Year = {2002}
}
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