Compiler and Architecture  for Superscalar and embedded Processors

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  • Team Head

    André SEZNEC
    tel: +33 2 99 84 73 36
    fax: +33 2 99 84 25 28
    e-mail :


    Project Assistant

    Evelyne LIVACHE
    tel: +33 2 99 84 73 34


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    Research themes


    Project presentation

    CAPS is a common project from INRIA, CNRS, the University of Rennes 1 and the INSA of Rennes.

    The Caps team studies both hardware and software issues for the design of high performance computer systems. Peak computer performance grows steadily, however this peak performance increase is obtained through ever rising hardware complexity. Several parallelism levels are now used in hardware, and high performance can only be reached through the simultaneous usage on all these levels on applications. Then tuning performance on applications is becoming a very high-tech activity. Researches on the Caps team aim at efficiently exploiting the various levels of parallelism available in machines while hiding most of the hardware complexity to the user.

    Our research in computer architecture aims at improving the behavior of the memory hierarchy and at increasing the instruction level parallelism that can be extracted by the hardware. We have proposed a few innovative structures of cache memories (e.g. skewed caches and decoupled sectored caches) which help to reduce the gap between main memory access time and processor clock. We are involved in research for improving the throughput of the pipeline front-end in superscalar processor (branch prediction for instance). We are also investigating SMT approach where several processes (either dependent or independent) share the functional unit from a superscalar execution core.

    On the othe hand, the path for performance relies also on the software management of instruction level parallelism and of memory hierarchy. We are studying techniques to detect and improve data and instruction locality. Scheduling techniques (software pipeline, loop unrolling, ...) are developped to submit more instruction level parallelism to the hardware. These techniques are applied on general purpose processors as well as on embedded processors (multimedia for instance).

    Hiding the software complexity of performance tuning from the user is a  major issue. Therefore, a significant part of our activity is dedicated to the development of user friendly performance tuning environments.


    View the project presentation


    Activity report