Table des matières
CAPS team
CAPS members
CAPS themes
CAPS Grail
CAPS path to the Grail
Need for high-performance processors
CAPS (ancient) background
CAPS background in architecture
CAPS background in compilers
We build on
Salto overview
Compiler activities
Computer aided hand tuning
CAHT
Analysis and Tuning tool for Low Level Assembly and Source code (with Thomson Multimedia)
ATLLAS - Analysis and Tuning tool for Low Level Assembly and Source code : Tuning method
Assembly Level Infrastrure for Software Enhancement (with STmicroelectonics)
ALISE
ALISE
Preprocessor for media processors (MEDEA+ Mesa project)
Preprocessor for media processors: our approach
Iterative compilation
High performance instruction set simulation
ABSCISS: Assembly Based System for Compiled Instruction Set Simulation
Enabling superscalar processor simulation
Calvin2 + DICE
Moving tools to IA64
Low power, compilation, architecture, … (just beginning :=)
Caches and branch predictors
Simultaneous Multithreading
« Enlarging » the instruction window (supported by Intel)
Unwritten rule on superscalar processor designs
4-cluster WSRS architecture (supported by Intel)
Multiprocessor on a chip
HIPSOR HIgh Performance SOftware Random number generation
HIPSOR (2)
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