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Multi-clock reconfigurable architectures

Place: 
Context: 

In avionic or automotive fields, critical real-time embedded systems coordinate iterative and/or sporadic tasksthat may vary during system operation due to external conditions (eg flight phases of an airplane, or operation phases of a car...) or/and internal ones (for example degraded mode). In the end, for some systems, we can imagine hot reconfigurations, motivated by error corrections, changes in their environment, or evolution of functionalities. But these architectural evolutions should be made while preserving security properties linked to the criticality of these systems.

In the particular case of the streamed dataflow model of computation, a higher-order, purely functional domain-specific language such as CAPH has been proposed for programming stream-processing applications on reconfigurable hardware such as FPGAs.

On the other hand, synchronous languages (and among them Signal, which also allows a design with independent or weakly constrained clocks) make it possible to guarantee security properties in a static architecture framework.

Mission: 

The proposed post doctoral aims to take advantage of both the generality of the dataflow model as it is taken into account by CAPH and the properties of the synchronous languages (and in particular Signal) to define a new language, or model, adapted for multi-clock reconfigurable architectures.

This model could be an extension of the polychronous model of the Signal language and of the CCSL standard, allowing a more powerful language than usual Signal, but preserving its safety properties. The designed language or model will be provided with a rich type system including behavioral properties considered as types: refinement types. Its formal (operational) and type semantics will be defined, along with type transformation operations (casting operations in the form of interface synthesis) will be provided.

References

[1] Paul Le Guernic, Jean-Pierre Talpin, and Jean-Christophe Le Lann. Polychrony for system design. Journal for Circuits, Systems and Computers, Special Issue on Application Specific Hardware Design, World Scientific, April 2003.

[2] Jean-Pierre Talpin and David Nowak. A synchronous semantics of higher-order processes for modeling reconfigurable reactive systems. International Conference on Foundations of Software Technology and Theoretical Computer Science (FST & TCS’98), Springer-Verlag, Lecture Notes in Computer Science, 1998.

[3] Louis Mandel and Marc Pouzet. ReactiveML, a Reactive Extension to ML. Principles and Practice of Declarative Programming (PPDP 2005).

[4] Jocelyn Sérot and François Berry. High-Level Dataflow Programming for Reconfigurable Computing. IEEE 26th International Symposium on Computer Architecture and High Performance Computing, October 2014.

[5] J.-P. Talpin, P. Jouvelot, S. Shukla. Towards refinement types for time-dependent data-flow networks. ACM-IEEE Conference on Methods and Models for System Design. IEEE, 2015.

Required Diploma: 
Thesis
Lieu de travail: 
RENNES
Type of contrat: 
POST-DOC
Durée du contrat (en mois): 
18
Quotité: 
100%
Salary (before tax) / Month €: 
Salary according to experience
Date prévisionnelle d'embauche: 
Sunday, 1. July 2018
Date prévisionnelle d'embauche: 
Le plus tôt possible
Date limite de candidature: 
Monday, 30. April 2018
How to apply: 

Please send your applications by mail to : Thierry Gautier, thierry.gautier[at]inria.fr