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    • André SEZNEC

    Head of CAPS Team

     

    contact information

    IRISA
    Campus de Beaulieu
    35042 RENNES Cedex
    FRANCE 

    tel : +33 2 99 84 73 36
    fax : +33 2 99 84 71 71

    e-mail: seznec@irisa.fr
     
     

    who am I?

    I am "directeur de recherches" at IRISA/INRIA in Rennes. Since 1994, I have been the head of the CAPS (Compiler  and Architecture for Embedded and Superscalar Processors) team at IRISA/INRIA.

    I have been conducting research on high performance computer architecture at IRISA/INRIA since 1983. 

    I got a Doctorat-ès-Sciences from University of Rennes I in 1987. 

    Till 2004, I was the only European on the hall of fame of ISCA

    From february 1999 to february 2000, I  was with the Alpha group at Digital/Compaq.
     
     

    research interests

    As a programmer I am fundamentally a sequential guy, and it seems that the overwhelming majority of the programmers are like me: they are programming sequential algorithms, may be manipulating parallel objects. Therefore my researches in computer architecture have essentially focussed on providing performance for this class of programmers, mainly on a single processor. Here is a list of topics I have been active for a few years: 

    technological watch on microprocessors

    From 1991 to 1998, I have been conducting technogical watch on microprocessors with the support of the french ministry of defense. 

    Technological Surveys on Microprocessors (in French)
     
     

    most significant publications

    Ph.D. dissertation
    1. A.Seznec "Contribution à l'étude des multiprocesseurs fortement pipelinés" Thèse d'état, Université de Rennes I, juin 1987 

    International journals 

    1. Y.Jégou, A.Seznec, "Data Synchronized Pipeline Architecture : pipelining in multiprocessor environment" Journal of Parallel and Distributed Computing, Dec. 1986 (also Proceedings International Conference on Parallel Processing 1986 (ACM), St-Charles, Illinois Aug. 1986) 
    2. A.Seznec, "A new interconnection network for SIMD computers : The Sigma network" IEEE Transactions on Computers, July 1987 
    3. A. Seznec, J. Lenfant, ``Interleaved Parallel Schemes'', IEEE Transactions on Parallel and Distributed Systems, Dec 1994. 
    4. A. Seznec, J. Lenfant, ``Odd memory systems: A new approach'', Journal of Parallel and Distributed Computing, May 1995. 
    5. N. Drach, A. Gefflaut, P. Joubert, A. Seznec, ``About cache associativity in low-cost shared memory multi-microprocessors'', Parallel Processing Letters, Sept. 1995 (also IRISA Report No 760)
    6. A. Seznec, ``Decoupled Sectored Caches'', IEEE Transactions on Computers, Feb. 1997 
    7. F. Bodin, A. Seznec, ``Skewed Associativity improves performance and enhances predictability'', IEEE Transactions on Computers, May 1997 
    8. E. Rohou, F. Bodin, C. Eisenbeis, A. Seznec, "Handling Global Constraints in Compiler Strategy", International Journal of Parallel Programming, august 2000.
    9. P. Michaud, A. Seznec, S. Jourdan, ``An exploration of instruction fetch requirement in out-of-order superscalar processors'', International  Journal of Parallel Programming, March 2001
    10. A. Seznec, N. Sendrier, "HAVEGE: a user-level software heuristic for generating empirically strong random numbers", 2003, to appear in the special issue on "Random number generation and highly uniform point sets" of ACM Transaction on Modeling and Computer Simulations, October 2003 , postscript (209 Kb), pdf (278 Kb)
    11. R. Dolbeau, A. Seznec, CASH: revisiting hardware sharing in single-chip parallel processor , Journal of Instruction Level Parallelism , April 2004
    12. A. Seznec , ``Concurrent Support of Multiple Page Sizes on a Skewed Associative TLB'', IEEE Transactions on Computers, July 2004 
    13. Julio César Hernández Castro, José María Sierra, André Seznec, Antonio Izquierdo, Arturo Ribagorda: The strict avalanche criterion randomness test. Mathematics and Computers in Simulation 68(1): 1-7 (2005)
    14. A.Seznec, "Genesis of the OGEHL predictor", Journal of Instruction Level Parallelism , April 2005
    15. A. Seznec,  R. Espasa      ``Conflict-free accesses to strided vectors on a banked cache", IEEE Transactions on Computers, July 2005, the associated C program to compute conflict free slices"
    16. A. Seznec, P. Michaud, `` A case for (partially) tagged Geometric History Length Branch Prediction", Journal of Instruction Level Parallelism , Feb. 2006, associated TAGE simulator (gzipped)
    17. Olivier Rochecouste and Gilles Pokam and André Seznec,,  A Case for a Complexity-Effective, Width-Partitioned Microarchitecture.   ACM Transactions on Architecture and Code Optimisation (TACO), Volume 3 , Issue 3, September 2006.
    18. A. Seznec  "The L-TAGE predictor",     Journal of Instruction Level Parallelism, May 2007
    19. A. Seznec   "The idealistic GTL predictor",   Journal of Instruction Level Parallelism, May 2007
    20. P.Michaud, Y. Sazeides, A. Seznec, T. Constantinou, D. Fetis, "A study of thread migration in temperature-constrained multicores", ACM Transactions on Architecture and Code Optimization, Volume 4, Issue 2, June 2007
    21. H. Vandierendonck, A. Seznec,   "Fetch Gating Control through Speculative Instruction Window Weighting", Transactions on High-Performance Embedded Architectures and Compilation. Vol. 2 (2). 2007. pp. 19-39
    22. K. De Bosschere, G. Gaydadjiev, X. Martorell, N. Navarro, M. O’Boyle, D. Pnevmatikatos, A. Ramirez, P. Sainrat, A. Seznec, P. Stenstrom, and O. Temam. High-Performance Embedded Architecture and Compilation Roadmap. In Transactions on High-Performance Embedded Architectures and Compilers. Vol 1, No 3. Dec. 2006
    Book chapter
    1. T. Lafage, A. Seznec, "Choosing Representative Slices of Program execution for  Microarchitecture Simulations: A Preliminary Application to the Data Stream", Workload Characterization of Emerging Applications, Kluwer Academic Publishers,  also  Workshop on Workload Characterization (WWC 2000),  september 2000.
    MAJOR CONFERENCES
    Architectural Support on Programming Languages and Operating Systems (ASPLOS) 
    1.  A. Seznec, S.Jourdan, P. Sainrat, P. Michaud, `` Multiple-Block Ahead Branch Predictors'', Proceedings of the 7th conference on Architectural Support for Programming Languges and Operating Systems, Boston, October 1996 
    International Symposium on Computer Architecture (ISCA) 
    1. A.Seznec, "An efficient routing control unit for the Sigma network" Proceedings of the 13th International Symposium on Computer Architecture (IEEE-ACM) Tokyo, June 1986, 
    2. A.Seznec, Y.Jégou "Synchronizing processors through memory requests in a tightly coupled multiprocessor" Proceedings of the 15th International Symposium on Computer Architecture (IEEE-ACM), Honolulu, June 1988 
    3. A.Seznec, J. Lenfant "Interleaved Parallel Schemes: improving memory throughput on vector supercomputers" Proceeding of the 19th International Symposium on Computer Architecture (IEEE-ACM), Queensland, May 1992 
    4. A. Seznec, ``A case for two-way skewed-associative cache'', Proceedings of the 20th International Symposium on Computer Architecture(IEEE-ACM), San Diego, May 1993 
    5. A. Seznec, J. Lenfant, ``Odd Memory Systems may be quite interesting'', Proceedings of the 20th International Symposium On Computer Architecture (IEEE-ACM), San Diego, May 1993 
    6. A. Seznec, ``Decoupled sectored caches: reconciliating low tag volume and low miss ratio'', Proceedings of the 21th International Symposium on Computer Architecture(IEEE-ACM), Chicago, april 1994 
    7. F. Bodin, A. Seznec, "Skewed-associativity enhances performance predictability",Proceedings of the 22th International Symposium on Computer Architecture (IEEE-ACM), Santa-Margharita, june 1995 (also IRISA Report No 909 ) 
    8. A. Seznec, ``Don't use the page number, but a pointer to it'', Proceedings of the 23rd International Symposium on Computer Architecture (IEEE-ACM), Philadelphie, may 1996.
    9. P.Michaud, A. Seznec, R. Uhlig, `` Trading conflict and capacity aliasing in conditional branch predictors '', Proceedings of the 24th International Symposium on Computer Architecture (IEEE-ACM), Denver, june 1997 
    10. A. Seznec, S. Felix,  V. Krishnan,  Y.  Sazeides , "Design trade-offs on the EV8 branch predictor", Slides (Powerpoint) ,  Proceedings of the 29th International Symposium on Computer Architecture (IEEE-ACM),  Anchorage,  may 2002
    11. R. Espasa, F. Ardanaz, J. Emer, S. Felix, J. Gago, R. Gramunt, I. Hernandez, T. Juan, G. Lowney, M. Mattina, A. Seznec, "Tarantula: A vector Extension to the Alpha Architecture",  Proceedings of the 29th International Symposium on Computer Architecture (IEEE-ACM),  Anchorage,  may 2002
    12. A. Seznec, A. Fraboulet, "Effective ahead pipelining of instruction block address generation",  Proceedings of the 30th International Symposium on Computer Architecture (IEEE-ACM),  San Diego,  june 2003
    13. A. Seznec, ``Analysis of the OGEHL predictor", Proceedings of the 32th International Symposium on Computer Architecture (IEEE-ACM),  Madison,  june 2005
    International Symposium on Microarchitecture 
    1. A.Seznec, K.Courtel "Controlling and sequencing an heavily pipelined floating-point operator", Proceedings of the 25th IEEE International Symposium on Microarchitecture (MICRO 25), Portland, Dec. 1992 
    2. N. Drach, A. Seznec, ``MIDEE: Smoothing Branch and Instruction Cache Miss Penalties on Deep Pipelines'', Proceedings of the 26th International Symposium on Microarchitecture (ACM-IEEE), Austin, december 1993 (also RR INRIA 2038) 
    3. A. Seznec, E. Toullec, O. Rochecouste ``Register Write Specialization Register Read Specialization: A Path to Complexity Effective of Wide Issue Superscalar Processors'', Slides (Powerpoint) , Proceedings of the 35th International Symposium on Microarchitecture (ACM-IEEE), Istambul, November 2002 
    International Symposium on High Performance Computer Architecture 
    1. A. Seznec,"DASC cache", Proceedings of the First High Performance Computer Architecture(IEEE), Raleigh (USA), January 1995 (also RR INRIA 2082) 
    2. S. Hily, A. Seznec `` Out-Of-Order Execution May Not Be Cost-Effective on Processors Featuring Simultaneous Multithreading'',Proceedings of the Fiftht High Performance Computer Architecture(IEEE), Orlando (USA), January 1999, longer version available as IRISA Report No 1179, March 1998 
    3. P. Michaud, A. Seznec, "Data-flow prescheduling for large instruction windows in   out-of-order processors",Proceedings of the 7th international Conference on High Performance  Computer Architecture
    International Conference on Parallel Archictectures and Compiler Techniques 
    1. N. Drach, A. Seznec, D. Windheiser,``Direct-mapped versus set-associative pipelined caches'', Proceedings of PACT' 95 (Parallel Architectures and Compiler Techniques), Chypre, June 1995 (also IRISA Report No 803) 
    2. S. Hily, A. Seznec `` Branch prediction and simultaneous multithreading'', Proceedings of PACT' 95 (Parallel Architectures and Compiler Techniques), Boston, October 1996  
    3. D. Truong, F. Bodin, A. Seznec, `` Improving Cache Behavior of Dynamically Allocated Data Structures'' Proceedings of PACT'98, Paris , october 1998
    4. P. Michaud, A. Seznec, S. Jourdan, "Exploring Instruction-Fetch Bandwidth requirement in Wide-Issue Superscalar Processors", International  Conference on Parallel Architectures and Compilation Techniques, Newport Beach, October 12-16, 1999. 
    International Conference on Parallel Processing 
    1. Y.Jégou, A.Seznec, "Data Synchronized Pipeline Architecture : pipelining in multiprocessor environment" , Proceedings International Conference on Parallel Processing 1986 (ACM), St-Charles, Illinois Aug. 1986 
    2.  A.Seznec, Y.Jégou "Optimizing memory throughput in a tightly coupled multiprocessor" Proceedings International Conference on Parallel Processing 1987 (ACM), St-Charles, Illinois, Aug. 1987
    3. N. Drach, A. Seznec, ``Semi-Unified Caches'', Proceedings of the International Conference on Parallel Processing, St Charles, Illinois, Aug. 1993 
    International Conference on Supercomputing 
    1. A.Seznec, Y.Jégou "Towards a large number of processors in a tightly coupled multiprocessor using no cache" Proceedings of the International Conference on Supercomputing (ACM), Saint-Malo, July 1988 
    2. Y.Jégou, A.Seznec, "An Asynchronous Buffering Network for Tightly Coupled Multiprocessors" Proceedings of the International Conference on Supercomputing (ACM), Heraklion, June 1989
    Other international conferences
    1. Y.Jégou, A.Seznec "The DSPA multipipeline" Working Conference on Parallel Processing (IFIP), Pise, April 1988  
    2. A. Seznec, F. Bodin, ``Skewed-associative caches'', Proceedings of PARLE' 93, Munich, June 1993  
    3. A. Seznec, ``About set and skewed associativity on second level caches'', Proceedings of the International Conference on Computer Design, Boston, October 1993 
    4. Bas Aarts, Michel Barreteau, François Bodin, Peter Brinkhaus, Zbigniew Chamski, Henri-Pierre Charles, Christine Eisenbeis, John R. Gurd, Jan Hoogerbrugge, Ping Hu, William Jalby, Peter M.W. Knijnenburg, Michael F.P. O'Boyle, Erven Rohou, Rizos Sakellariou, Henk Schepers, André Seznec, Elena A. Stöhr, Marco Verhoeven, Harry A.G. Wijshoff "OCEANS: Optimizing Compilers for Embedded HPC Applications" Proceedings of Europar'97 - August 1997 Lecture Notes in Computer Science 1300 - Springer Verlag
    5. Michel Barreteau, François Bodin, Peter Brinkhaus, Zbigniew Chamski, Henri-Pierre Charles, Christine Eisenbeis, John R. Gurd,Jan Hoogerbrugge, Ping Hu, William Jalby, Peter M. W. Knijnenburg, Michael F. P. O'Boyle, Erven Rohou, Rizos Sakellariou, André Seznec, Elena Stöhr, Menno Treffers, Harry A. G. Wijshoff: OCEANS: Optimising Compilers for Embedded Applications. Euro-Par 1998: 1123-1130
    6. Michel Barreteau, François Bodin, Zbigniew Chamski, Henri-Pierre Charles, Christine Eisenbeis, John R. Gurd, Jan Hoogerbrugge,Ping Hu, William Jalby, Toru Kisuki, Peter M. W. Knijnenburg, Paul van der Mark, Andy Nisbet, Michael F. P. O'Boyle, Erven Rohou, André Seznec, Elena Stöhr, Menno Treffers, Harry A. G. Wijshoff: OCEANS - Optimising Compilers for Embedded Applications. Euro-Par 1999: 1171-1175
    7. Thierry Lafage, André Seznec, Erven Rohou, François Bodin: Code Cloning Tracing: A ``Pay per Trace'' Approach. Euro-Par 1999: 1265-1268
    8. Thierry Lafage, André Seznec: Combining Light Static Code Annotation and Instruction-Set Emulation for Flexible and Efficient On-the-Fly Simulation (Research Note). Euro-Par 2000: 178-182
    9. Kun Luo, Manoj Franklin, Shubhendu S. Mukherjee, André Seznec: Boosting SMT Performance by Speculation Control. IPDPS 2001: 2
    10. Julio César Hernández Castro, José María Sierra, André Seznec: The SAC Test: A New Randomness Test, with Some Applications to PRNG Analysis. ICCSA (1) 2004: 960-967
    11.  Amaury Darsch, André Seznec: IATO: A Flexible EPIC Simulation Environment. SBAC-PAD 2004: 58-65
    12. G. Pokam, O. Rochecouste, A. Seznec, F. Bodin ``Speculative Software Management of Datapath-width for Energy Optimization'', LCTES'04, June 2004
    13. H. Vandierendonck,  A. Seznec, Fetch Gating Control through Speculative Instruction Window Weighting,  High Performance Embedded Architectures and Compilers. 2007. pp. 120-135
    14.  Thomas Piquet, Olivier Rochecouste and André Seznec, Exploiting Single-Usage for Effective Memory Management    ACSAC,  Seoul, August 2007.

    Some workshops and newsletter papers.

    1. N. Drach, A. Seznec,: Semi-Unified Caches: Increasing Associativity of On-Chip Caches, IEEE TCCA Newsletter, 1993
    2. A.Seznec, F. Lloansi, ``About effective miss penalty on out-of-order microprocessor'', IRISA Report No 970 November 1995 (a slightly modified version appears as: A. Seznec, F. Lloansi ``Performance impact of the L2 contention on out-of-order execution superscalar processors'', IEEE TCCA NEWSLETTER, March 1997)
    3. D. Truong, F. Bodin, A. Seznec "Accurate Data Layout May Boost Cache Performance, in Workshop on interaction between compilers and computer architecture Feb 1, 1997 San Antonio, and in IEEE TCCA NEWSLETTER june 1997
    4. E. Rohou, F. Bodin, A. Seznec et. al, ''SALTO : System for Assembly-Language Transformation and Optimization'', PI IRISA 1032 (129 Kb) July 1996, also Sixth Workshop on Compilers for Parallel Computers - December 1996 
    5. S. Hily, A. Seznec `` Standard Memory Hierarchy Does Not Fit Simultaneous Multithreading, Proceedings of MTEAC'98 Workshop, Feb. 1998, a longer version is available as Contention on 2nd Level Cache May Limit The Effectiveness of Simultaneous Multithreading, 22 pages, IRISA Report No 1086, Feb. 1997 
    6. F.Bodin, Z. Chamski, C. Eisenbeis, E. Rohou, A. Seznec GCDS: A Compiler Strategy for Trading Code Size Against Performance in Embedded Applications , 3rd Intl. Workshop on Code Generation for Embedded Processors, Witten - Germany, March 1998. 
    7. A. Djabelkhir, A. Seznec, ``Characterization of embedded applications for decoupled processor architecture'', Workshop on Workload Characterization (WWC 2003), october 2003
    8. A. Seznec, The O-GEHL Branch Predictor  CBP-1, December 2004
    9. T. Constantinou, Y. Sazeides, P. Michaud, D. Fetis, A. Seznec, "Performance Implications of Single Thread Migration on a Chip Multi-Core", ACM SIGARCH Computer Architecture News, volume 33, issue 4, November 2005.
    10. A. Seznec ``Looking for limits in branch prediction with the GTL predictor'', ppt presentation, CBP-2, December 2006
    11. A. Seznec ``A 256 Kbits L-TAGE predictor'', ppt presentation, CBP-2, December 2006
    A few "interesting" research reports (I would still recommend them)
    1. A. Seznec A New Case for Skewed-Associativity", 23 pages, IRISA Report No 1114, July 1997 
    2. P. Michaud, A. Seznec, S. Jourdan, P. Sainrat Alternative Schemes for High-Bandwidth Instruction Fetching , IRISA Report No 1180, March 1998 
    3. A. Seznec, P. Michaud Dealiased Hybrid Branch Predictors , IRISA Report No 1229, Feb. 1999 
    4. P. Michaud, A. Seznec, A comprehensive study of dynamic global history branch prediction , IRISA Report No 1406, June 2001
    5. A. Seznec, N. Sendrier, " HArdware Volatile Entropy Gathering and Expansion: generating unpredictable random numbers at user level",IRISA Report, October 2002
    6. A. Seznec, Redundant History Skewed Perceptron Predictors: pushing limits on global history branch predictors , IRISA Report No 1554, sept. 2003
    7. A. Seznec, Revisiting the perceptron predictor , IRISA Report No 1620, May 2004 
    Technological watch on microprocessors (in french, from 1992 to 1997, all you want to know on the microarchitecture on the  processors of these days) 
    1. P. Laporte, A. Seznec, `` Etude comparative des microprocesseurs MIPS R3000, SPARC Version 7 et IBM Power : Architectures et Performances '', Feb. 1992 (99 pages, postscript, 99 kO) 
    2. A. Seznec, A.M. Kermarrec, T. Vauléon `` Etude Comparée des Architectures des Microprocesseurs MIPS R4000, DEC 21064 et T.I. SUPERSPARC '', Dec. 1992 (102 pages, postscript, 223kO) 
    3. A. Seznec, T. Vauléon, `` Etude comparative des architectures des microprocesseurs Intel Pentium et Power PC 601 '', June 1994 (109 pages, postscript, 230kO) 
    4. A. Seznec, Y. Mével, `` Etude des architectures des microprocesseurs IBM Power2, DEC 21164 et MIPS R8000 '', June 1995 (128 pages, postscript, 325kO) 
    5. A. Seznec, Y. Mével`` Evolutions des gammes de processeurs xxx86, MIPS Rxxx, Sparc, PowerPC et DEC Alpha '', Dec. 1995 (110 pages, postscript, 298kO) 
    6. A. Seznec, F. Lloansi`` Etude des architectures des microprocesseurs MIPS R10000, UltraSparc et PentiumPro '', Mai 1996 (122 pages, postscript, 328 kO) 
    7. A. Seznec, T. Lafage`` Evolutions des gammes de processeurs MIPS Rxxx, Dec Alpha, PowerPC, Sparc, x86 et PA-Risc '', Juin 1997 (158 pages, postscript, 520 kO) 
    Patents
    1. Cache memory device
    2. Method for ensuring maximum bandwidth on accesses to strided vectors in a bank-interleaved cache
    3. Conflict free parallel read access to a bank interleaved branch predictor in a processor