Optimizing register file structure for wide issue dynamic order
execution superscalar processors
Localisation : Irisa, Rennes
Equipe(s) : Caps
Responsable : André Seznec (tél. direct :
02 99 84 73 36, email : seznec@irisa.fr)
The path for performance on superscalar processors should combine
instruction level parallelism with high clock frequency. However,
constructors are facing obstacles for implementing both features.
For instance, a very high clock frequency is enabled through very
deep pipeline on Intel Pentium 4 while Alpha EV8 will feature a
very wide instruction level parallelism and SMT parallelism with
a less aggressive clock.
The register file is one of the piece which limits clock frequency
on a wide issue superscalar processor. This register file is central
in a superscalar processor. Assuming N instructions or micro-operations
per cycle, each consuming (up to) two operands and producing (up
to) one result, the register file should support 2N reads and N
writes per cycle. Deep pipelines and wide instruction issuing enlarges
the depth of speculation in processors. Then, large number of physical
registers are needed. Unfortunately the silicon area, the power
consumption and the access time of the register file all increase
with the number of write and read ports on the register file as
well as with the number of physical registers.
Research propositions to improve access time, silicon area and
power consumption on the register file includes the virtual-physical
register file (limits the number of physical registers) , register
caching (caching the critical register) and the use of two function
units clusters (duplicates the register file, but halves the number
of read ports).
We propose to investigate new solutions to reduce the number of
ports in a register file for a wide-issue superscalar (and SMT)
processor , to increase the possible instruction level parallelim
exploited with a fixed number of ports in a register file and/or
to decrease the number of physical registers needed.
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