ISA support and Out-of-Order execution
Localisation : Irisa, Rennes
Equipe(s) : Caps
Responsable : André Seznec (tél. direct :
02 99 84 73 36, email : seznec@irisa.fr)
Sujet : While the superiority of RISC ISAs (e.g. Alpha,
Mips, Sparc ..) over CISC ISAs (e.g. x86) has been clear for single
issue pipelined processors and for in-order execution superscalar
processors, complex out-of- order execution mechanisms have smoothened
(even annihilated) the benefits of RISC ISAs for current generation
processors.
The path for higher performance using current ISAs seems to be
more and more speculative execution (branches, memory dependencies,
data, ..). On the other hand, support for part of this speculative
execution can be provided by the ISA as in the new EPIC instruction
set IA64 from Intel/HP. IA 64 implements new concepts (at least
for general purpose computing) for speculative execution (predicated
execution and advanced loads). These mechanisms allow to expose
to the compiler a part of the speculative execution that is managed
by hardware on current out-of-order execution superscalar processors.
Itanium, the first IA64 processor will execute instructions in-order,
but future generation IA64 processors will implement out-of-order
execution.
The goal of the proposed study is to evaluate ISA supports for
speculative executiom in the light of state-of- the-art out-of-
order execution mechanisms. This will allow to focus computer architecture
work and compiler design to focus on the really useful mechanisms
in both world and eliminate (neglect) those that are better traeted
on the other sideonly complexify. In particular, the use of predicated
execution and advanced loads seem to allow to limit/simplify the
hardware needed for out-of-order execution, but raises new questions:
how predicate execution compare with branch prediction? should the
predicates also be predicted ? which kind of branches must be respectively
treated by hardware and software ? should (in)dependency between
memory accesses be treated through software or hardware ?
As it features speculative execution support, the IA64 instruction
set will be used as a research vehicle for this study. A simulation
platform for the microarchitecture will be required. This platform
must allow detailed and performant simulation. Such a simulator
for out-of-order execution processors is very slow (10000-100000
slower than a real processor). In practice, only the beginning of
the application is simulated. CAPS team at IRISA/INRIA has developped
an approach called Calvin2 mixing direct fast execution (at host
performance) and simulation. This approach allows to simulate samples
distributed over a whole real size application. This approach has
been developped on an UltraSparc platform. No simulation platform
for the IA64 ISA is currently available. Definition and design of
such a platform will be part of the project. Calvin2 will be ported
on an IA64 platform and a simulation library for out-of-order execution
processors will developped for this platform. The simulation platform
will be then distributed to the scientific community.
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