Static WCET analysis

Knowing task worst-case execution times (WCET) is of prime importance for the timing analysis of hard real-time systems.

Timing analysis is in general made of two levels : WCET analysis and schedulability analysis. WCET analysis considers the time requirements of an isolated task. At this level, activities other than ones related to the considered task are ignored. Tasks are assumed to never block (blocking is dealt with by the schedulability analysis). At the upper level (i.e. the schedulability analysis level) multiple tasks execute on the processor and compete for resources, and thus may block while attempting to access the resources.The tightness of schedulability analysis relies on the accuracy of the WCET analysis.

Static WCET analysis, thanks to the static analysis of a piece of source code, returns an upper bound on the time required to execute it on a given hardware.

Several mechanisms that use modeling and simulate some architectural feature behaviors such as instruction cache, branch prediction mechanisms and pipeline Static WCET analysis is complicated due to the presence of architectural features that improve the performances of the processor such as instruction cache, branch prediction and pipeline. Taking into account modern architectural features makes it possible to determine tight WCET bounds. On a given architecture, it is possible thanks to the modeling of modern architectural features.

We have designed a static WCET analysis tool named Heptane that takes into account the three above-mentioned architectural features for a Pentium processor.