Thomas Chabrier

thomas.chabrier@irisa.fr

IRISA-ENSSAT, 6 rue Kerampont, BP80518, 22305 Lannion cedex, France
(+33) (0)2 96 46 92 10

Presentation

    Ph.D. Student in computer science since October 2009
    Title :  Reconfigurable Arithmetic Units for Cryptoprocessors with Protection against Side Channel Attacks
    Supervisors : Arnaud Tisserand and Emmanuel Casseau
    Grant : Brittany region and CG22 (Conseil Général 22)
    I am member of the IRISA laboratory and the CAIRN research group

    Full curriculum vitae in French or English

    Research Topics

Arithmetic operators
Circuit design (ASIC, FPGA)
Cryptography
Security

    Ph.D. Thesis Abstract
           In public-key cryptography, RSA or elliptic curve cryptography (ECC), arithmetic is a key element for designing efficient and secure cryptosystems. Finite fields arithmetic should be fast to perform computations on a large amount of operations (additions, substractions, multiplications, inversions in the field) on large numbers (160-500 bits for ECC and 1024-4096 bits for RSA). For cost reasons, arithmetic operators should also be area, memory and power efficient. And for security reasons, they should not reveal internal informations at run time using physical attacks such as side channel analysis.
            In this PhD thesis, we will study, design in hardware, validate (at theorical and practical levels) and compare various arithmetic operators for high-speed and low-power public-key cryptosystem with a high robustness against observation attacks. We will work on arithmetic algorithms and various representations of numbers for the field GF(p). Some algorithms and/or representations of numbers may have specific characteristics to reduce current signature at execution time. This may be used as countermeasures against side channel attacks. Speed and power consumption of the various operators will be theoretically estimated and practically evaluated on FPGAs. We will also physically evaluate the cryptoprocessor robustness against side channel attacks (SPA, DPA, high-order DPA...). For this, we will use the attack lab developed in the team (high-speed oscilloscope, active probes, low-noise power supply, dedicated server for traces analysis and attack scheduling, specific FPGA cards). We will focus on GF(p) operators for elliptic curves. The arithmetic operators developed during the PhD thesis will be integrated into an ECC cryptoprocessor which is developed in the CAIRN team.

News and events

Conferences 2011

May: Crypto'Puces (Porquerolles, France), SYMPA (St-Malo France)
April: C2 (St Pierre d'Oléron, France)

Conferences 2010

November: Conference on Signals, Systems, and Computers (Asilomar, Pacific Grove, CA, US)
June: CryptArchi (Paris, France)
May: Coding and Cryptography Workshop (Cork, Ireland)
March: ECOFAC (Plestin les Grèves, France)

Teaching

DUT Mesures Physiques, Lannion, 1ère et 2ème année, informatique d'instrumentation (TD + TP 44h)
IUT Lannion, 1ère année, C2I (Certificat Informatique et Internet) (20h)

Undergraduate Students co-advisor

Claudiu Chirap (Technical University of Cluj-Napoca, Romania), Tools for a Cryptoprocessor on Elliptic Curves, June-Septembre 2010, IRISA, ERAMUS Grant, advisor : A. Tisserand

Publications

T. Chabrier, D. Pamula and A. Tisserand. Hardware implementation of DBNS recoding for ECC processor. Asilomar Conference on Signals, Systems and Computers, Pacific Grove, CA, USA, Nov. 7-10, 2010.
A. Tisserand, T. Chabrier , D. Pamula. Arithmetic Level Countermeasures for ECC Coprocessor. Claude Shannon Institue Workshop on Coding and Cryptography, Cork, Ireland, 2010