News

Research

Topics of interest

My research activities focus on the design and the management of Dynamically Reconfigurable Architectures (DRA). More precisely I investigate the following areas:
  • New approaches in dynamically reconfigurable architecture (HW point of view),
  • Design of efficient and flexible interconnections,
  • Dedicated embedded operating system for DRA,
  • Fault-tolerant systems,

Abstract of my activities

The research that I address focuses on the design of dynamically reconfigurable systems. Constant evolution of applications and the ever-increasing need for performances require the development of new efficient and flexible architectures. These constraints have led to more complex architectures, their reconfiguration mechanisms and management. In the first part of my work, we propose architectures providing a good compromise between performance, power consumption, and flexibility. To simplify the design of these architectures and their management, we have proposed a high-level description language that allows generating the architecture but also setting up its development flow. The modern SoCs include a large number of heterogeneous features, and face problems due to technology shrink. To meet these challenges, the concept of integrated network on silicon seems promising. In my second line of research, we are studying new coding and new technologies to reduce consumption of interconnect while improving their reliability. We are also working to define flexible networks adapted to the dynamic reconfiguration paradigm. The emergence of reconfigurable systems requires the use of specific tools and mechanisms. In particular, the presence of a dedicated operating system becomes necessary. It would provide services such as tasks scheduling, communications management and provide a model independent of the target architecture for applications deployment. This is the topic of the third axis of my research activities. The second issue of this axis is the need to develop fault-tolerant architectures. Thus the establishment of specific management can develop reliable dynamically reconfigurable systems.

Projects

  • 2011-2013: FlexTiles project. European FP7 Project
  • 2011-2013: ARDyT Architecture Reconfigurable Dynamiquement Tolérante aux fautes. ANR ARPEGE Project
  • 2010-2012: ARF project Architecture Reconfigurable Fiable. “Défis scientifiques émergents” de l’Université de Rennes 1
  • 2009-2011: FosFor (Flexible Operating System FOr Reconfigurable platform) ANR ARPEGE Project
  • 2009-2011: CIFAER (Communications Intra-véhicule et Architecture Embarquée Reconfigurable) ANR ARPEGE Project

Students

Current Ph.D. students

  • Romain Brillu (2011-2014): Heterogeneous multicore architecture supporting unified programming model.
  • Antoine Eiche (2009-2011): Ordonnancement temps réels pour architectures hétérogènes à partir de structures de réseaux de neurones.
  • Istas Pratomo (2010-2013): Supports dynamiques de communications : vers la définition d’un NoC adaptatif dans un SoC reconfigurable.

Ph.D. Graduates

Recent Publications

Full list of publications. Sorted by year.
See also:
Publications of Pillement & Year: 2011 [rss]
Books Chapters
[2011] Vehicular Technologies (F. Nouvel, P. Tanguy, S. Pillement, M. Pham), Chapter in Experiments of in-vehicle power line Communications (Katarina Lovrecic, ed.), Intech, 2011. (Accepted for publication) [bib]
Articles
[2011] Reconfigurable ECU communications in AUTOSAR Environment (M. Pham, S. Pillement), Chapter in Ingnieurs de l'Automobile, SIA, volume 813, 2011. [bib]
[2011] Real-Time Scheduling on Heterogeneous System-on-Chip Architectures Using an Optimized Artificial Neural Networks (D. Chillet, A. Eiche, S. Pillement, O. Sentieys), In Journal of Systems Architecture, volume In Press, Accepted Manuscript, 2011. [bib] [pdf] [doi]
International Conference Papers
[2011] A Framework for the Design of Reconfigurable Fault Tolerant Architectures (M. Pham, S. Pillement, S. Le Nours, O. Pasquier), In DASIP, 2011. [bib]
[2011] Hardware OS Communication Service and Dynamic Memory Management for RSoCs (S. Narayanan, D. Chillet, S. Pillement, I. Sourdis), In ReconFig, 2011. [bib]
[2011] Communication Service for hardware tasks executed on dynamic and partial reconfigurable resource, (S. Narayanan, L. Devaux, D. Chillet, S. Pillement, I. Sourdis), In Conference on Very Large Scale Integration (VLSI-SoC), 2011. [bib]
[2011] Parallel Evaluation of Hopfield Neural Networks (A. Eiche, D. Chillet, S. Pillement, O. Sentieys), In NCTA, 2011. [bib]
[2011] Error Recovery Technique for Coarse-Grained Reconfigurable Architectures (M. Azeem, S. Piestrak, O. Sentieys, S. Pillement), In IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems, 2011. [bib]
International Workshop Papers
[2011] Re2DA: Reliable and Reconfigurable Dynamic Architectures (M. Pham, L. Devaux, S. Pillement), In Workshop on Reconfigurable Communication-Centric SoCs (ReCoSoC), 2011. [bib]
[2011] A design methodology for specification and performances evaluation of Network On Chip (D. Adrouche, R. Sadoun, S. Pillement), In IEEE International Workshop on Reliability Aware System Design and Test, 2011. [bib]
National Conference Papers
[2011] Modélisation et implémentation de calculateurs reconfigurables tolérants aux fautes et communications flexibles intra-véhicules (M. Pham, S. Pillement, S. Le Nours, O. Pasquier), In Symposium en Architecture de machines (SympA), 2011. [bib]
[2011] Implémentation matérielle dun réseau de neurones pour lordonnancement temporel de tâches sur architecture reconfigurable (A. Pasturel, A. Eiche, D. Chillet, S. Pillement, O. Sentieys), In Symposium en Architecture de machines (SympA), 2011. [bib]
[2011] Exploitation du concept de tolérance aux fautes des réseaux de neurones pour la résolution de problèmes d'optimisation (D. Chillet, A. Eiche, S. Pillement, O. Sentieys), In GRETSI, 2011. [bib]
Powered by bibtexbrowser

Teaching

Since september, 1999, I am associate professor at the IUT of Lannion of the University of Rennes 1. I teach Computer Science and Electronics in the Physical Measurements department. I teach especially computer architecture and software programming (algorithmics and langage) and digital and analog electronics.

Course materials (mainly in french):

Where and how to contact me

My email: Sebastien.Pillement AT irisa.fr
ENSSAT - Université de RENNES 1
Equipe CAIRN
BP 447 - 6 Rue de Kerampont
22305 LANNION - FRANCE
Tel : +33 (0)2-96-46-91-66
Fax : +33 (0)2.96.46.90.75
Bureau : 307N
 IUT de Lannion - Université de RENNES 1
Département Mesures Physiques
BP 30219 - Rue Edouard Branly
22302 LANNION - FRANCE
Tel : +33 (0)2-96-46-94-85