Danuta Pamula 

PhD student electronics/computer science - cotutelle thesis, 

Silesian University of Technology, Faculty of Automatic Control, Electronics and Computer Science, Institute of Electronics, Division of Digital and Microprocessor Systems, Gliwice, Poland (since October 2008)

IRISA-ENSSAT, Lannion, France (since October 2009)

PhD info:

: Arnaud Tisserand (France) and Edward Hrynkiewicz (Poland) 
Grant : BGF - Boursier de Gouvernement Francais (French Government Grant holder)
Member of:  the IRISA laboratory and the CAIRN research group, IEEE Student Member

Draft Title:

Arithmetic operators on GF(2^m) for cryptographic applications: performance - power consumption - security tradeoffs.

Ph.D. Thesis description:

        In public-key cryptography, RSA or elliptic curve cryptography (ECC), arithmetic is a key element for designing efficient and secure cryptosystems. Finite fields arithmetic should be fast to perform computations on a large amount of operations (additions, subtractions, multiplications, inversions in the field) on large numbers (160-500 bits for ECC and 1024-4096 bits for RSA). For cost reasons, arithmetic operators should also be area, memory and power efficient. And for security reasons, they should not reveal internal informations at run time using physical attacks such as side channel analysis.

In this PhD thesis, we will study, design in hardware, validate (at theoretical and practical levels) and compare various arithmetic operators for high-speed and low-power public-key cryptosystem with a high robustness against observation attacks. We will work on arithmetic algorithms and various representations of numbers for the extensions of the binary field GF(2^m). Some algorithms and/or representations of numbers may have specific characteristics to reduce current signature at execution time. This may be used as countermeasures against side channel attacks. Speed and power consumption of the various operators will be theoretically estimated and practically evaluated on FPGAs. We will also physically evaluate the cryptoprocessor robustness against side channel attacks (SPA, DPA, high-order DPA...). For this, we will use the attack lab developed in the team (high-speed oscilloscope, active probes, low-noise power supply, dedicated server for traces analysis and attack scheduling, specific FPGA cards). We will focus on GF(2^m) operators for elliptic curves. An ECC cryptoprocessor is developed in the CAIRN team.

Another PhD student and one research of the team are also working on this cryptoprocessor. The arithmetic operators developed during the PhD thesis will be integrated into this cryptoprocessor.

Plan overview:

  • bibliography on arithmetic operators, side channel attacks and countermeasures
  • study and design of basic GF(2^m) operators: addition, subtraction, multiplication and inversion
  • operators validation (at design time and execution time using FPGA emulation)
  • comparison of the operators performance (speed, power consumption and current signature variations)
  • documentation and publication of the designed operators
  • operators integration in the ECC cryptoprocessor developed in CAIRN (2 PhD students, 1 faculty and several trainees)
  • performances evaluation of the cryptoprocessor - evaluation of the cryptosystem robustness using side channel attacks (using CAIRN's attack lab)
  • study and design of arithmetic countermeasures using various representations of numbers and arithmetic algorithms
  • arithmetic countermeasures validation and performance evaluation
  • robustness evaluation using side channel attacks
  • analysis, documentation and publication of the attacks results
The last 4 steps will be repeated as much as possible during the thesis.

Research areas:

Circuit design (FPGA, ASIC)

Arithmetic Operators

Security and Cryptography


Publications and projects:

    1. Participation in R&D project no. WKP_1/1.4.1/1/2005/14/14/231/2005 "Moduły wideo detektorów pojazdów ZIR-WD do sterowania i nadzoru ruchu  drogowego"( „Video detector modules ZIR-WD”), conducted at Silesian University of Technology, Faculty of Transport, Katowice, Poland
    2. D.Pamuła, A.Ziębiński. Implementation of MD5 algorithm., IFAC Workshop on Programmable Devices and Embedded Systems preprints, PDES 2009, p.45-50, Roznov pod Radhostem, Czech Republic
    3. J.Flak, D.Pamuła, A.Ziębiński. Using programmable array to process the geological phenomena data., Geology and Information Technology seminar 2009 (GIT), XVI Komputer Networks(Sieci Komputerowe) Conference
    4. D.Pamuła, A.Ziębiński. Implementacja generatora funkcji skrótu MD5 w strukturze FPGA, „Systemy czasu rzeczywistego. Postępy badań i zastosowania”, Wydawictwo Telekomunikacji i Łączności, praca zbiorowa edited by Zbigniew Zieliński, Systemy Czasu Rzeczywistego(Real Time Systems) Conference 2009, Pułtusk
    5. D.Pamuła, A.Ziebinski. Securing video stream captured in real time. PRZEGLĄD ELEKTROTECHNICZNY (Electrical Review), ISSN 0033-2097, R. 86 NR 9/2010 
    6. A. Tisserand, T. Chabrier , D. Pamula. Arithmetic Level Countermeasures for ECC Coprocessor. The Claude Shannon Institue Workshop on Coding and Cryptography, Cork, Ireland, 2010
    7. D.Pamuła, E.Hrynkiewicz, A.Tisserand. Multiplication in GF(2m): area and time dependency/efficiency/complexity analysis. PDES 2010 : Programmable Devices and Embedded Systems, Oct 2010, Pszczyna, Poland
    8. T. Chabrier, D. Pamula and A. Tisserand. Hardware implementation of DBNS recoding for ECC processor. Asilomar Conference on Signals, Systems and Computers, Nov. 7-10, 2010, Pacific Grove, California, USA



Silesian University of Technology, Faculty of Automatic Control, Electronics and Computer Science:

  • Introduction to Electronics (lab) - course in English
  • Microprocessor Systems (lab) - course in Polish
  • Circuit theory and Electronics (lab) - course in Polish
  • Computer programming - course in Polish

  Silesian University of Technology Faculty of Automatic Control, Electronics and Computer Science  inria irisa Universite de Rennes 1 opis 2 obrazka