Automatic synthesis of secure & predictable processors for the Internet of Thing

Publié le mer 25/01/2023 - 22:01
Unité de recherche
IRISA - UMR 6074
Description du sujet de la thèse

The vast majority of automotive and IoT platforms rely on low-power Micro-Controller Units, whose micro-architecture and instructions sets are highly customized. These customized processors are designed by hand using Hardware Description Languages. Designing a processor pipeline at this level of abstraction is very tedious, and extremely time-consuming.

The ability to automatically infer a micro-architecture (or family of microarchitecture) from a more abstract representation (e.g. a behavioral model of the processor ISA in C/C++) can be an answer to these issues, as it could streamline the design process while enabling early design space exploration. Unfortunately, current commercial High Level Synthesis flows, which translate C/C++ to hardware designs, are unable to efficiently deal with such inputs, because they lack the ability to take advantage of speculation. Recent research results have however shown that this limitation could be lifted and that it was possible to automatically generate processor pipelines whose performance and area cost were comparable to manual designs, as demonstrated by the SpecHLS flow developed at IRISA.

New design issues are however emerging: in addition to performance and energy constraints, IoT hardware platforms must now also integrate security and predictability guarantees. Such guarantees are very challenging to enforce, as they involve a deep understanding of the underlying micro-architecture along with often subtle (and ad-hoc) changes to the HDL design. They can therefore only be implemented by domain experts, and only at the price of significant additional design efforts. Such non-functional guarantees also often adversely impact performance and hardware cost. As a consequence, choosing the best design involves a trade-off between conflicting requirements, and design time constraints often force designers to opt for sub-optimal solutions.

The goal of the thesis is to study and propose novel techniques for micro-architectural synthesis, in which non-functional properties are supported through domain specific analysis (for predictability) and transformations (for security). Because of its open license and growing popularity, the project will focus on the open-source RISC-V ISA.

  1. Jonathan Bachrach, Huy Vo, Brian Richards, Yunsup Lee, Andrew Waterman, Rimas Avižienis, John Wawrzynek, and Krste Asanović. “Chisel: constructing hardware in a scala embedded language”. In: DAC Design automation conference2012. IEEE. 2012, pp. 1212–1221.

  2. Benjamin Binder, Mihail Asavoae, Belgacem Ben Hedia, Florian Brandner, and Mathieu Jan. “Is This Still Normal? Putting Definitions of Timing Anomalies to the Test”. In: IEEE 27th International Conference on Embedded and Real-Time Computing Systems and Applications (RTCSA). 2021, pp. 139–148.

  3. Thomas Chamelot, Damien Couroussé, and Karine Heydeman. “SCI-FI – Control Signal, Code, and Control Flow Integrity against Fault Injection Attacks”. In: DATE. 2022.

  4. Elke De Mulder, Samatha Gummalla, and Michael Hutter. “Protecting RISC-V against Side-Channel Attacks”. In: DAC. 2019.

  5. Jean-Michel Gorius, Simon Rokicki, and Steven Derrien. “Design Exploration of RISC-V Soft-Cores through Speculative High-Level Synthesis”. In: Proc. of the 2022 international conference on Field Programmable Technology. Dec. 2022.

  6. Jean-Michel Gorius, Simon Rokicki, and Steven Derrien. “SpecHLS: Speculative Accelerator Design Using High-Level Synthesis”. In: IEEE Micro 42.5 (2022), pp. 99–107.

  7. Alban Gruin, Thomas Carle, Hugues Cassé, and Christine Rochange. “Speculative Execution and Timing Predictability in an Open Source RISC-V Core”. In: Real-Time Systems Symposium. IEEE, 2021, .

  8. Lana Josipović, Andrea Guerrieri, and Paolo Ienne. “Speculative Dataflow Circuits”. In: Proceedings of the 2019 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays. FPGA ’19. Seaside, CA, USA: Association for Computing Machinery, 2019, pp. 162–171.

  9. Gai Liu, Joseph Primmer, and Zhiru Zhang. “Rapid generation of high-quality RISC-V processors from functional instruction set specifications”. In: 2019 56th ACM/IEEE Design Automation Conference (DAC). IEEE. 2019, pp. 1–6.

  10. Eriko Nurvitadhi, James C Hoe, Timothy Kam, and Shih-Lien L Lu. “Automatic pipelining from transactional datapath specifications”. In: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 30.3 (2011).

Liste des encadrants et encadrantes de thèse

Nom, Prénom
Derrien Steven
Type d'encadrement
Directeur.trice de thèse
Unité de recherche
Architectures des processeurs embarqués, Synthèse de Circuits, Compilation