Lieu / Conference location

CNRS
Délégation Paris Michel-Ange
3 rue Michel-Ange
75794 Paris cedex 16
Tél. 01 44 96 40 00
Auditorium Marie-Curie

Plan d'accès / Access

8:30

9:00

Accueil et enregistrement des participants

Ouverture du Forum
Michel Dayde, délégué scientifique CNRS / INS2I en charge des grilles de calcul et du HPC

9:05

9:15

9:45

10:15

Introduction sur les formations
Serge Petiton, directeur, bureau de l'ORAP

Le point sur les nouveaux masters

Le point sur les labels

Témoignage d'un ancien doctorant : son parcours

Pascal Havé, responsable technique de projet, IFP

Table ronde
animée par Mathieu Vidard, journaliste, animateur de "La tête au carré" le magazine scientifique de France Inter

Les thèmes retenus :
Carrrières et débouchés
Formations permanentes en HPC
Formations initiales

Les participants :
Violaine Louvet, Université de Lyon 1
Vincent Levillain, ASTRIUM
Toufik Abboud, IMACS
Pascal Dauboin, TOTAL
William Jalby, UVSQ

GPU Acceleration: a Fad or the Yellow Brick Road onto Exascale?

Satoshi Matsuoka, Tokyo Institute of Technology

Abstract

Since the first commodity x86 cluster Wigraf achieving paltry 10s~100s Megaflops in 1994,  we  have experienced several orders of magnitude boost in performance. However, the first Petaflop was achieved with the LANL RoadRunner, a Cell-based "accelerated" cluster, and in 2010 we may see the first (GP)GPU-based cluster reaching Petaflops. Do such  non-x86"accelerator" merely push the flops superficially, or are they fundamental to scaling? Based on experiences from TSUBAME, the first GPU-accelerated cluster on the Top500, we show that GPUs not only achieve higher performance but also better scaling, and in fact their true nature as multithreaded massively-parallel vector processor would be fundamental for Exascale. Such results are being reflected onto the design of TSUBAME2.0 and its successors.

Biography

Satoshi Matsuoka is a full Professor at the Global Scientific Information and Computing Center (GSIC) of Tokyo Institute of Technology (Tokyo Tech). He is the technical leader in the construction of the TSUBAME supercomputer, which became the fastest supercomputer in Asia-Pacific in June, 2006, and continued to be Japan's #1 for 4 consecutive Top 500s during June 2006 - May 2008. He  is also one of the pioneers of Grid computing research in Japan, and in particular co-lead the Japanese NAREGI project, whose aim was to develop and foster research grid infrastructure in Japan. Currently he is designing TSUBAME2, which will be heavily GPU accelerated and will likely be the first Petaflops supercompuer in Japan. He has chaired many ACM/IEEE international conferences, including the technical papers chair role for SC09. He has won many awards including the JSPS Prize from the Japan Society for Promotion of Science in 2006, from his Majesty Prince Akishinomiya, for the first time as a Computer Scientist.

From Bits to Buildings: Energy Efficiency and the Path to Exaflops Computing
Horst Simon, NERSC Berkeley

Abstract

In a recent survey by IDC, facilities managers named power and  cooling by an overwhelming majority to be the most pressing issues of  concern to them. A study of Exaflops computing came to the conclusion that by projecting todays technology, an Exaflops computer might require 120 MW of power, if it can be built at all. A different study commissioned by the EPA estimates that power consumption by servers doubled in the period from 2000 to 2005 worldwide, and that total amount of electricity consumed  by servers world wide now costs about $7.2 B. This is already today the same order of magnitude as the the investment in HPC technology ($9.2B). We have thus reached a critical threshold that should give us cause to consider the question of power consumption as a potentially limiting factor to the future growth in HPC. I will try to address this very question: what are the power limitations of current technology, and how can we change the equation to assure the future rapid growth of HPC performance without contributing even more to carbon emissions and global warming. In particular, I will discuss several research projects that we have started in Berkeley to address the issue of reducing power consumption in HPC, both at the systems and at the building level.

Biography

Horst Simon is Associate Laboratory Director at Lawrence Berkeley National Laboratory for Computing Sciences and the Division Director for the Computational Research Division and Adjunct Professor of Computer Science at the University of California, Berkeley. His research interests are in the development of sparse matrix algorithms, algorithms for large-scale eigenvalue problems, and domain decomposition algorithms. His recursive spectral bisection algorithm is a breakthrough in parallel algorithms. He was also honored with the 1988 Gordon Bell Prize. He has served as a senior manager for Silicon Graphics, the Computer Sciences Corporation, Boeing Computer Services, and has been a member of the faculty at the State University of New York. He is currently a member of the advisory boards of more than five research organizations located throughout the world and is a member of many journal editorial boards and one of four editors of the twice-yearly “TOP500” list of the world’s most powerful computing systems.

16:00

Towards Petascale: Application and Benchmarking Activities in the PRACE Project

Mark Bull, EPCC - Edimbourg

Abstract

This talk will describe the activities of the PRACE project in the area of optimising and scaling applications in preparation for the installation of European petascale computers. It will also cover the development of the PRACE application benchmark suite, and will provide a look forward to the activities planned for the next phase of the project.

17:15

Clôture du forum