Security of Emerging On-Chip Interconnects

Subject
Since few years we are witnessing the emergence of manycore architectures, namely to the implementation of massive parallelism on a single chip. Associated with the shrinking size of the transistors, these manycore architectures should reach the integration of thousands of heterogeneous cores allowing huge parallel computation capabilities suitable for high-performance embedded computing systems and HPC. 
To satisfy the increase of on-chip communication requirements of theses architectures [1], technology evolution has allowed for the integration of silicon photonics and wireless communications on chip, thus leading to Wireless Network-on-Chip (WiNoC) [2-3] and Optical Network-on-Chip (ONoC) [4-5] paradigms. 
As technology advances and the use of emerging on-chip interconnects increases, the need for secure design and implementation becomes increasingly critical [6]. Indeed, as on-chip interconnects are used to transfer data and instructions between different components within a system-on-a-chip (SoC), these interconnects are vulnerable to a variety of attacks, such as side-channel attacks and fault injection attacks, which can compromise the security of the entire system. As a result, securing on-chip interconnects is becoming an important design concern for developers and manufacturers of SoCs. This includes implementing security measures such as encryption, and fault tolerance to protect against potential threats and maintain the integrity of the system.

The scope of the PostDoc position is relatively open and applicants are expected to identify the direction that suits them the most as a function of their background and interest. The goal is to improve the security of emerging on-chip interconnects in the context of manycore architectures, and we seek to find systematic methods to answer the key questions:

• What are the main weaknesses on emerging on-chip interconnect such as ONoC or WiNoC?
• How to detect and locate attacks on emerging on-chip interconnects?
• How to improve the robustness against security threats?

Bibliography
[1]    A. Karkar et al. “A Survey of Emerging Interconnects for On-Chip Efficient Multicast and Broadcast in Many- Cores”. In: IEEE Circuits and Systems Magazine 16., pp. 58–72 , 2016.
[2]    M. F. Chang, et al., “CMP Network-on-Chip Overlaid with Multi-Band RF-Interconnect,” Proc. of IEEE Int. symposium on High- Performance Computer Architecture (HPCA), pp. 191-202, 2008.
[3]    J.  Ortiz Sosa, O. Sentieys, C. Roland. A Diversity Scheme to Enhance the Reliability of Wireless NoC in Multipath Channel Environment. Twelfth IEEE/ACM International Symposium on Networks-on-Chip (NOCS), Oct 2018, Torino, Italy. pp.1-8
[4]    A. Shacham, K. Bergman, and L. P. Carloni. "Photonic networks-on-chip for future generations of chip multiprocessors." IEEE Transactions on Computers, vol. 57.9 pp: 1246-1260, 2008.
[5]    J. Luo, C. Killian, D. Chillet, S. Le Beux, I. OConnor, O. Sentieys. “Offline optimization of wavelength allocation and laser power in nanophotonic interconnects”. In: ACM Journal on Emerging Technologies in Computing Systems (JETC) (2018). 
[6]    S. Pasricha, J. Jose and S. Deb, "Electronic, Wireless, and Photonic Network-on-Chip Security: Challenges and Countermeasures," in IEEE Design & Test, vol. 39, no. 6, pp. 90-98, Dec. 2022, doi: 10.1109/MDAT.2022.3203017.