4th Intl WORKSHOP ON WORST-CASE EXECUTION TIME (WCET) ANALYSIS

Catania, Sicily, Italy, June 29, 2004
http://www.irisa.fr/wcet2004

in conjunction with the
16^th Euromicro Intl Conference on Real-Time Systems
Catania, Sicily, Italy, June 30 - July 2, 2004

Workshop program

Predictable Timing Behavior by using Compiler Controlled Operations
V. Hirvisalo, S. Kiminki, University of Helsinki, Finland

Simplifying WCET Analysis by Code Transformations
H. S. Negi, A. Roychoudhuri, T. Mitra, National University of Singapore

Optimizing JVM Object Management Operations to Improve WCET Predictability
A. Corsaro, C. Santoro, University of Washington, USA and University of Catania, Italy

Discussion

Influence on Onchip Scratchpad Memories on WCET
L. Wehmeyer, P. Marwedel, University of Dortmund, Germany

Controlling the influence of PCI DMA transfers on WCET of real-time software
J. Stohr, A. von Bullow, G. Farber, Technische Universitaet Muenchen, Germany

Synergetic effects in cache related preemption delays
J. Staschulat, R. Ernst, Technische Universitaet Braunschweig, Germany

Component-wise Instruction Cache Behavior Prediction (extended abstract)
A. Rakib, O. Parshin, S. Thesing, R. Wilhelm, Max Plank instut fur informatik and Universität des Saarlandes, Germany

Discussion

A Distributed WCET Computation Scheme for Smart Card Operating Systems
N. Aissa, C. Rippert, D. Deville, G. Grimaud, University of Lille, France

Inspection of industrial code for syntactical loop analysis
C. Sandberg, Mälardalen University, Sweden

A New Timing Schema for WCET Analysis
S. Petters, A. Betts, G. Bernat, University of York, UK

Petri Net Level WCET Analysis
F. Stappert, University of Paderborn, Germany

Measurement-Based Worst-Case Execution Time Analysis using Automatic Test-Data Generation
R. Kirner, P. Puschner, I. Wenzel, TU Vienna, Austria

Discussion