Catania, Sicily, Italy, June 29, 2004

in conjunction with the
16th Euromicro Intl Conference on Real-Time Systems
Catania, Sicily, Italy, June 30 - July 2, 2004


Workshop program


08:30 - 09:00 Registration

9:00 - 10:30 Session 1: Compiler and run-time optimizations for WCET determination (session chair: Raimund Kirner, TU Vienna, Austria)

Predictable Timing Behavior by using Compiler Controlled Operations
V. Hirvisalo, S. Kiminki, University of Helsinki, Finland

Simplifying WCET Analysis by Code Transformations
H. S. Negi, A. Roychoudhuri, T. Mitra, National University of Singapore

Optimizing JVM Object Management Operations to Improve WCET Predictability
A. Corsaro, C. Santoro, University of Washington, USA and University of Catania, Italy


10:30 - 11:00 Break

11:00 - 13:00 Session 2: Low-level analysis (session chair: Stefan Petters, Univ. of York, UK)

Influence on Onchip Scratchpad Memories on WCET
L. Wehmeyer, P. Marwedel, University of Dortmund, Germany

Controlling the influence of PCI DMA transfers on WCET of real-time software
J. Stohr, A. von Bullow, G. Farber, Technische Universitaet Muenchen, Germany

Synergetic effects in cache related preemption delays
J. Staschulat, R. Ernst, Technische Universitaet Braunschweig, Germany

Component-wise Instruction Cache Behavior Prediction (extended abstract)
A. Rakib, O. Parshin, S. Thesing, R. Wilhelm, Max Plank instut fur informatik and Universität des Saarlandes, Germany


13:00 - 14:30 Lunch break

14:30 - 16:30 Session 3: WCET calculation methods (session chair: Jan Gustafsson, Univ. of Mälardalen, Sweden)

A Distributed WCET Computation Scheme for Smart Card Operating Systems
N. Aissa, C. Rippert, D. Deville, G. Grimaud, University of Lille, France

Inspection of industrial code for syntactical loop analysis
C. Sandberg, Mälardalen University, Sweden

A New Timing Schema for WCET Analysis
S. Petters, A. Betts, G. Bernat, University of York, UK

Petri Net Level WCET Analysis
F. Stappert, University of Paderborn, Germany

Measurement-Based Worst-Case Execution Time Analysis using Automatic Test-Data Generation
R. Kirner, P. Puschner, I. Wenzel, TU Vienna, Austria


16:30 - 17:00 Break

Due to the character of the workshop the times given in this schedule might differ slightly.

For further details concerning the technical program of the workshop, please contact the program chair:

Isabelle Puaut
Campus universitaire de Beaulieu
35042 Rennes Cedex, FRANCE
Phone: +33 2 99 84 73 10
Email: puaut@irisa.fr