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D3 - ARCHITECTURE

Responsable: Olivier Sentieys (Université de Rennes 1)
Equipes: CAIRN, GRANIT, PACAP

Description en anglais.

Research on architectures and compilers for high-performance and embedded computing is also evolving quickly and the past decade has seen the emergence of small-scale multi-core processors. These multi-cores are now becoming mainstream for both general-purpose and embedded computing. This surge of small-scale multi-core processors has re-boosted the interest for research on architectures of multi-core processors as well as on techniques to exploit such multi-core architectures. Future generations of multi-cores will feature hundreds of cores and will include both homogeneous and heterogeneous solutions.

The main purpose of the Architecture Department is to propose new architectures and optimizing compiler environments for both general purpose and embedding computing platforms. In the context of domain-specific system-on-chip, we are also concerned with the interaction between architectures and applications, especially with stringent constraints such as low power consumption or limited resources. Finally, energy and power consumption issues are increasingly important and challenging constraint in both high performance and embedded markets. The need for energy efficient designs is crucial for applications such as green computing, green networking and green radio.

Therefore, research activities developed in the Architecture Department are dedicated to:

  • discovering new microprocessor architectural design to improve application performance, energy efficiency, dependability, and scalability,
  • inventing code generation techniques that ensure that software can exploit innovative designs and also efficient computer-aided design tools for automatic hardware design,
  • proposing application-specific designs or optimizing algorithms under specific constraints like limited resources or power, by analysing the interaction between architectures and applications.

The Architecture Department regroups researchers and experts in micro-architecture, software/compiler optimization, real-time systems, signal processing and computer-aided design.

Rapports d'activités (pdf)

CAIRN
2011 ; 2012 ; 2013 ; 2014 ; 20152016
GRANIT
2016 ;
PACAP
2016 ;
Ex-ALF : 2010 ; 2011 ; 2012 ; 2013 ; 2014 ; 2015

Séminaires/Workshops - Soutenances

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Soutenances thèses/HDR

Date Type Titre Orateur Lieu
18 déc 2017 Thèse Runtime Optimization Of Binary Through Vectorization Transformations Nabil HALLOU (PACAP) IRISA Rennes, Salle Petri-Turing