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Séminaire sécurité des systèmes électroniques embarqués

Date: 
Vendredi, 2. décembre 2016 -
10:30 - 12:30
Département: 
Orateur: 
Paolo MAISTRI et Franck COURBON
Lieu: 
IRISA Rennes - Campus de Beaulieu, 263 Av. du général Leclerc, Entrée bât 12F, Salles Pétri-Turing

2 décembre 2016

10h30-11h30

Paolo Maistri (TIMA Laboratory, Univ. Grenoble Alpes/CNRS, F-38031 Grenoble)

Hardware Design of Error Detection Schemes for Symmetric Ciphers

Secure hardware implementations are often used to accelerate cryptographic implementations; however, designers are well aware that cost and performance are not their only goal. Attacks exploiting side channel leakage or faulty behaviour are a serious threat that do not always require expensive equipment to be carried out, and can affect both symmetric and public-key cryptosystems. Hardware implementations must hence adopt solutions in order to make these attacks harder.
In this talk we will present a few schemes aiming at detecting faulty computations in symmetric ciphers, with a particular focus on the Advanced Encryption Standard. Two countermeasures will be primarily addressed: temporal redundancy based on a double-data rate computation scheme, and a parity-based error detection code automatically generated from the RTL structure of the design. Several experimental results will be provided in order to show the validity of the proposed approaches.

 

11h30-12h30

Franck Courbon (Computer Laboratory, University of Cambridge)

Scanning Electron Microscopy: a standard failure analysis tool for Hardware Trojan detection, localized fault attacks and memory contents extraction

In a more and more connected world, attacks target different payment, identification and transportation systems leading to various economic, social and societal impacts. Some of those attacks are directly based on embedded systems hardware structure. Thus, among others, attacks can profit from transistors' behavior or can aim to modify some part of an integrated circuit. Problematics behind Hardware Trojan detection, fault attacks and memory cell content extraction are addressed. Based on a 3 steps methodology, Sample preparation - Scanning Electron Microscopy (SEM) - Image processing, we depict how interesting Scanning Electron Microscopy intrinsic features are for hardware security. On one hand, after a frontside preparation down to transistors' active region, the methodology allows detecting malicious hardware modification, extracting memory contents from a type of ROM or locating individual transistors prior to a fault attack in a chip's synthesized logic. On the other hand, after a backside preparation down to transistors' tunnel oxides, the methodology allows retrieving Flash/EEPROM memory contents. The methodology is depicted with the help of practical experiments. We will particularly point out the cost, speed and efficiency advantages for such SEM based approaches.

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Prochaines séances (exposé(s) confirmé(s)) :

20 janvier 2017, 10h30-11h30, salle Petri/Turing

Maria Mendez ( Université de Bretagne-Sud / Lab-STICC )

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Autres annonces et calendrier : http://securite-elec.irisa.fr/