Supervisory Control Problem: Demo directory

Contents:

Directory contents

In this directory, you will find the following files and directory:

Unix:

Windows:

How to rebuild the complete demo

  1. Launch "polychrony" GUI and load vt.gpk file.
  2. Export le "internal" vt process as a textual file (for example vt.SIG as name).
  3. Compile the previous vt.SIG program with "z3z" option
    		 signal vt.SIG -z3z
                    
    It generates in the sub-directory vt/ the vt.z3z and vt_CMD.z3z files. See here for some modifications of vt.z3z file.
  4. Go to the vt subdirectory and call sigali tool execute (under sigali) the following commands
    	       ----------------
    	       set_reorder(2); 
                   read("vt_CMD.z3z");
                   quit();
    	       ----------------
    	     
    -> set_reorder(?) perform an automatic reordering of the underlying BDD. For some applications it is better to use set_reorder(1); (another kind of reordering).
  5. At this point, the files vt.sim and vt.res must have been generated.
  6. Goto the root directory of the example (i.e. up directory)
  7. Copy the vt.sim and vt.res (generated in 4) in the "current" directory.
  8. Under polychrony GUI, goto the vt_Foo process and load the resolver by the following command
    "Tools -> prove -> build_resolv " command.
    After this command, the file vt.SIG.SIG has been generated.
    IMPORTANT: Do not save the program (vt.gpk) after this action (as this program, contains some hidden lines of Signal code that have been automatically added)
  9. Use the "makeLib" command (see above). This compilation will basically produce a library that will be used further for the JAVA simulation. (The compiler will produce some C files in vt directory...)
  10. For simulate, execute the command
                    run_demo
                  

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