Head of team
Olivier SENTIEYS (Enseignant-chercheur, Université de Rennes 1)

CAIRN : Energy-Efficient Computing Architectures

The CAIRN project-team researches new architectures, algorithms and design methods for flexible, secure, fault-tolerant, and energy-efficient domain-specific computing architectures. Due to the performance and energy-efficiency requirements of system-on-chip (SOC), it becomes difficult to rely only on programmable processor solutions. To address this issue, we promote/advocate the use of reconfigurable hardware accelerators, which can offer higher performance at a lower energy cost, while preserving a high level of flexibility.

The team studies these systems from three angles:

  1. The design of new accelerator architectures with a focus on energy efficiency and fault tolerance.
  2. The development of their corresponding design flows (compilation and synthesis tools) to enable their automatic design from high-level specifications.
  3. Efficient management of different components in heterogeneous platforms




Creation date
Reporting institution
Université de Rennes 1, Inria, CNRS, ENS Rennes
Rennes (35) et Lannion (22)
Activity reports
Attachment Size
cairn2019.pdf 621.49 KB
cairn2018_0.pdf 906.06 KB
cairn2017_0.pdf 643.55 KB