UPaK

 
 

Participants:


C. Wolinski

IRISA/IFSIC, France


K.Kuchcinski

Lund University, Sweden


A. Postula

University of Queensland ,

Australia


Abstract:


    The developed prototype of UPaK system is designed to be a kernel of an automatic hardware synthesis as well as code and configuration generator for several architecture models. These models include processors with extended data-paths corresponding to extended instruction sets, processors with coarse grain reconfigurable systems tightly connected to data-paths, heterogeneous run-time coarse grain reconfigurable systems, and existing coarse grain reconfigurable systems.


    UPaK is implemented using advanced software technologies that include graph matching and flexible scheduling techniques recently developed by the authors. It is written in the Java language and therefore is a multi-platform tool.