Optimization of Routing in Programmable Processor Array Architectures

 
 

Participants:


C. Wolinski 

IRISA/IFSIC

France


Krzysztof Kuchcinski

Lund University

Sweden


Jurgen Teich, Frank Hannig

Univ. of Erlangen-Nurenberg

Germany


Abstract:


    We introduce a constraint programming based approach for the optimization of area and of reconfiguration time for communication networks for a class of regular 2D reconfigurable processor array architectures. For a given set of different algorithms the execution of which is supposed to be switched upon request at run-time, we provide static solutions for the optimal routing of data between processors. The routing found by our method minimizes the area or the reconfiguration time of the communication network, when switching between the execution of these algorithms. In fact, when switching, the communication network reconfiguration can be executed in just a few clock cycles. Moreover the communication network area can be minimized significantly.