Powerful Scalable LDPC coder architecture

 
 

Participants:


F.Charot C. Wolinski 

IRISA/IFSIC, France


N. Fau, F. Hamon

R-Interface

Marseille Innovation

Marseille


Abstract:


    We propose a new powerful scalable generic parallel and modular architecture well suited to LDPC code decoding.  The architecture is composed of several identical processing modules with their own local memories and a set of interconnection buses for inter-module communications. The input data blocks' distribution in between the different memory banks is made in such a way that the overall execution time which is a function of the data transfer (through the buses) is minimized. This is done with our optimization system based on a constraints programming approach.

This architecture template has been instantiated in the case of the 802.16e WiMax standard. The proposed design is fully compliant with all the code classes defined by the standard. It has been validated through the development of a cycle-accurate and bit-accurate SystemC simulation model and through its implementation on a Xilinx Virtex5 FPGA component. A four or six-module FPGA design yields a throughput ranging from 10 to 30 Mbit/s by means of 20 iterations at a clock frequency of 160 MHz which mostly satisfies communication throughput in the case of the WiMax Mobile communication.