Steven Derrien

Steven Derrien

Contact

IRISA
Campus de Beaulieu
35042 Rennes Cedex

tél : 02 99 84 74 60
fax : 02 99 84 71 71

e-mail: sderrien@irisa.fr

Position

Professor at ISTIC, University of Rennes 1.
Member of the CAIRN research group at IRISA/INRIA.

Job offers

Open European funded post-doc & post-doc positions (ALMA project).

Current research activities

Source to source program transformations for High Level Synthesis
Automatic parallelization for heterogeneous embeded many-core architectures
Ultra low-power architectures for Wireless Sensor Nodes

Current projects

FP7 project ALMA (2011-2014)
ANR project COMPA (2011-2014)

Publications

Habilitation (in english) :

Design Automation for Applictaion Specific Hardware Architectures. Habilitation à diriger les recherches de l'Université de Rennes 1, soutenue le 13 décembre 2011.

Phd dissertation (in french)

Etude quantitative des techniques de partitionnement de réseaux de processeurs pour l'implantation sur circuits FPGA , Thèse de l'université de Rennes 1, soutenue le 2 décembre 2002, pdf, transparents.

Book chapters :

Steven Derrien, Sanjay Rajopadhye, Patrice Quinton and Tanguy Risset. High-Level Synthesis of Loops Using the Polyhedral Model. In High-Level Synthesis: From Algorithm to Digital Circuit by Philippe Coussy and Adam Morawiec. Springer Netherlands, 2008.

Journal papers :

Naeem Abbas, Steven Derrien, Sanjay Rajopapdhye, and Patrice Quinton. Hardware Acceleration
of HMMER on FPGAs. 2011. Submitted to IEEE Transaction on parallel and Distributed
Computing, currently undergoing major revision.
Muhammad Adeel Pasha, Steven Derrien, and Olivier Sentieys. System Level Synthesis for
Wireless Sensor Node Controllers : A Complete Design Flow. ACM Transactions on Design
Automation of Electronic Systems, 17(1), 2012.
Vivek D. Tovinakere, Olivier Sentieys, and Steven Derrien. A Polynomial Based Approach to
Wakeup Time and Energy Estimation in Power-Gated Logic Clusters. Journal of Low Power
Electronics, 7 :482–489, december 2011.
Steven Derrien, Patrice Quinton: Hardware Acceleration of HMMER on FPGAs. Journal of Signal Processing Systems, issue 58, Springer : 53-67, 2010
Rayan Chikhi, Steven Derrien, Auguste Noumsi, Patrice Quinton. Combining flash memory and FPGAs to efficiently implement a massively parallel algorithm for content-based image retrieval, International Journal of Electronics, Volume 95 Issue 7,Pages 621 – 635, 2008

Steven Derrien, Alexandru Turjan, Claudiu Zissulescu, Bart Kienhuis and Ed Deprettere, ``Deriving Efficient Control in Process Networks with Compaan/laura'', to appear in the International Journal of Embedded Systems, to appear in 2005.

International conferences :

Antoine Morvan, Steven Derrien, and Patrice Quinton. Efficient Nested Loop Pipelining in
High Level Synthesis using Polyhedral Bubble Insertion. In International Conference on Field-
Programmable Technology (FPT’11), Beijing, China, 2011. December 2011.

Antoine Floch, Tomofumi Yuki, Clement Guy, Steven Derrien, Benoit Combemale, Sanjay
Rajopadhye, and Robert B. France. Model-Driven Engineering and Optimizing Compilers : A
bridge too far ? In ACM/IEEE 14th International Conference on Model Driven Engineering
Languages and Systems (Models’11), pages 608–622, October 2011.

Vivek T D, Olivier Sentieys, and Steven Derrien. A Semiemperical Model for Wakeup Time
Estimation in Power-Gated Logic Clusters. In Proc. of the IEEE/ACM Design Automation
Conference (DAC), Anaheim, CA, USA, June 2012.

V. Basupalli, Tomofumi Yuki, Sanjay V. Rajopadhye, Antoine Morvan, Steven Derrien, Patrice
Quinton, and David Wonnacott. ompVerify : Polyhedral Analysis for the OpenMP Programmer.
In 7th International Workshop on OpenMP, IWOMP 2011, pages 37–53, 2011.

Alexandre Cornu, Steven Derrien, and Dominique Lavenier. HLS Tools for FPGA : Faster
Development with Better Performance. In Reconfigurable Computing : Architectures, Tools
and Applications - 7th International Symposium, ARC 2011, pages 67–78, 2011.

Vivek T D, Olivier Sentieys, and Steven Derrien. Wakeup Time andWakeup Energy Estimation
in Power-Gated Logic Clusters. International Conference on VLSI Design, 0 :340–345, 2011.

Naeem Abbas, Steven Derrien, Sanjay Rajopadhye, and Patrice Quinton. Accelerating HMMER
on FPGA using Parallel Prefixes and Reductions. In IEEE International Conference on
Field-Programmable Technology (FPT’10), pages 37–44, Beijing, China, December 2010.

M. Adeel Pasha, Steven Derrien and Olivier Sentieys, A complete design-flow for the generation of ultra low-power wsn node architectures based on micro- tasking. in Proceedings of the IEEE/ACM Design Automation Conference (DAC 2010), June 2010

M. Adeel Pasha, Steven Derrien and Olivier Sentieys, System-Level Synthesis for Ultra Low-Power Wireless Sensor Nodes, to appear at 13th Euromicro Conference on Digital System Design: Architectures, Methods and Tools (DSD 2010), September 2010.

M. Adeel Pasha, Steven Derrien and Olivier Sentieys, Ultra Low-Power FSM for Control Oriented Applications, Proceedings of the IEEE International Symposium on Circuits and Systems, ISCAS 2009, Taipei, Taiwan

Steven Derrien, Patrice Quinton, Parallelizing HMMER for hardware acceleration on FPGAs, 18th IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP 2007), Montreal, July 2007 (best paper award)

Rayan chikhi, Steven Derrien, Auguste Noumsi, Patrice Quinton, Combining Flash Memory and FPGAs to Efficiently Implement a Massively Parallel Algorithm for Content-Based Image Retrieval, International Workshop on Applied Reonfigurable comuting, Brasil, March 2007.

Auguste Noumsi, Steven Derrien, Patrice Quinton, Acceleration of a Content Based Image Retrieval Application on the RDISK Cluster. IEEE International Parallel & Distributed Processing Symposium, April 2006.

Alain Darte, Steven Derrien, Tanguy Risset, Hardware/Software Interface for Multi-Dimensional Processor Arrays, IEEE International Conference on Application-specific Systems, Architectures and Processors, July 2005.

S.Derrien, A. Turjan, C.Zissulescu, B. Kienhuis, Deriving Efficient Control for Process Networks, Workshop on Systems, Architectures, Modeling, and Simulation (SAMOS), 2003.

D. Lavenier, S. Guyétant, S. Derrien, S. Rubini, A reconfigurable parallel disk system for filtering genomic banks, ERSA'03, Engineering of Reconfigurable Systems and Algorithms , Las Vegas, Nevada, USA, 2003.

S. Derrien, S. Rajopadhye, Energy/Power Estimation of Regular Processor Arrays, International Symposium on System Synthesis. Kyoto, Japan, October 2002..

S.Derrien, A.C.Guillou, P.Quinton, T.Risset and C.Wagner, Automatic Synthesis of Efficient Interfaces for Compiled Regular Architectures, Workshop on Systems, Architectures, Modeling, and Simulation (SAMOS), 2002. (ps.gz)

S. Derrien, S. Rajopadhye, S. Sur-Kolay, Combining Instruction and Loop Level Parallelism for Array Synthesis on FPGAs, International Symposium on System Synthesis. October 2001 (pdf).

S. Derrien, S. Rajopadhye, Loop Tiling for Reconfigurable Accelerators, International Conference on Field Programmable Logic, August 2001 (pdf).

D.lavenier, E.Fabiani, S.Derrien, C.Wagner, Systolic Array for computing the pixel purity index (PPI) algorithm on hyperspectral images, SPIE Conference on Imaging Spectrometry, 2001. (pdf) .

S. Derrien, K.G. Konolige, Approximating a Single Viewpoint in Panoramic Imaging Devices, IEEE International Conference on Robotic and Automation. April 2000.

S. Derrien, S. Rajopadhye, FCCMs and the Memory Wall, IEEE Symposium on FPGA Custom Computing Machines, April 2000.

S. Derrien, T. Risset, Interfacing compiled FPGA programs: the MMAlpha approach, International Workshop on Engineering of Reconfigurable Hardware/Software Objects, June 2000.

S. Derrien, S. Sur Kolay and S. Rajopadhye, Optimal Partitionning for FPGA based Arrays Implementation, (IEEE PARELEC'00 Trois-Rivières, Quebec), August 2000.

Research reports :

S. Derrien, S.Rajopadhye, S. Sur-Kolay : Combining Instruction and Loop Level Parrallelism for FPGAs. IRISA Research report N°1376, Frebruary 2001. .