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 Retargetable code generation for ASIPs

contacts:  F.  Charot, V. Messé

In a hardware-software co-design methodology, the hardware and software components of an embedded system are designed jointly. Once the designer has determined which parts of the system functionality will be implemented in hardware, and which parts in software, then each of the hardware and software components are designed separately using appropriate tools (hardware synthesis, code generation and hardware-software cosimulation tools). Depending upon the results of simulations, the original design specification may be re-repartitioned and the process reiterated until the system requirements are satisfied.

Embedded systems, increasingly include ASIPs (Application Specific Instruction Set Processors). The key advantage of these programmable components is a tradeoff between efficiency and flexibility since software allows late change in the design cycle and reuse of existing hardware components.

Retargetable code generation  tools play an crucial role in  the ASIP design process since many instruction set architectures have to be evaluated.  The target architecture may be changing in order to minimize cost, speed, code size, and power consumption and/or to increase performance of the whole system. This is achieved by designing its architecture, generating code for it, and then evaluating the code for desired performance.

The efficient design space exploration of candidate architectures requires the use of a flexible code generation framework. This framework must allow  different code generation flows  to be specified according to the features of the target architecture and the results of these flows to be compared. Our work aims at defining a code generation framework allowing the user to build specific compilation flows using a library of flexible modules.

The way the ASIP designer informs the compiler about the features of its processor architecture gave rise to the Armor processor description language.

our publications - january 1999