Publications 2004
Academic Journals
- Romain Dolbeau, André Seznec. CASH: Revisiting hardware sharing in single-chip parallel processor. Journal of Instruction Level Parallelism, April 2004.
- K. Heydemann, F. Bodin, P.M.W. Knijnenburg, L. Morin. UFS: a Global Trade-off Strategy for Loop Unrolling for VLIW Architectures. To appear in Concurrency and Computation: Practice and Experience Journal, 2004.
- G. Pokam, S. Bihan, J. Simonnet, F. Bodin. SWARP: A Retargetable Preprocessor for Multimedia Instructions. Concurrency and Computation: Practice and Experience, 16(2):303-318, 2004.
- Gilles Pokam, Sté Bihan, Simonnet Simonnet, Fran\cc Bodin. SWARP: a retargetable preprocessor for multimedia instructions. Concurrency and Computation: Prac\-tice and Experience, 16(2):303-318, 2004.
- A. Seznec. Concurrent support of multiple page sizes on a skewed associative TLB. IEEE Transactions on Computers, July 2004.
International Conferences
- Julio Cesar Hernandez, Pedro Isasi, André Seznec. On the design of state-of-the-art pseudorandom number generators by means of genetic programming. In Proceedings of the 2004 IEEE Congress on Evolutionary Computation, Pages 1510-1516, Portland, Oregon, 2004.
- Julio César Hern‡ndez, José Mar’a Sierra, André Seznec. The SAC Test: A New Randomness Test, with Some Applications to PRNG Analysis. In Proceedings of the International Conference Computational Science and Its Applications - ICCSA 2004, LNCS vol. 3043, Pages 960-967, April 2004.
- Amaury Darsch, Andre Seznec. IATO: A Flexible EPIC Simulation Environment. In Proceedings of the 16th Symposium on Computer Architecture and High Performance Computing (SBAC-PAD 2004), October 2004.
- L. David, I. Puaut. Static Determination of Probabilistic Execution Times. In Proc. of the 16th Euromicro Conference on Real-Time Systems, Pages 223-230, Catania, Sicily, Italy, July 2004.
- Pierre Michaud. Exploiting the cache capacity of a single-chip multi-core processor with execution migration. In Tenth International Symposium on High-Performance Computer Architecture, February 2004.
- Pierre Michaud. A PPM-like, tag-based branch predictor. In Proceedings of the First Workshop ChampionShip Branch Prediction in conjunction with MICRO-37, December 2004.
- Pierre Michaud. Exploiting the cache capacity of a single-chip multi-core processor with execution migration. In Tenth International Symposium on High-Performance Computer Architecture, February 2004.
- Gilles Pokam, François Bodin. Exploring the energy-efficiency potential of a phase-based cache resizing scheme for embedded systems. In Proceedings of the 8th Annual Worskhop on Interaction between Compilers and Computer Architectures (INTERACT-8), February 2004.
- G. Pokam, F. Bodin. An Offline Approach for Whole-Program Paths Analysis using Suffix Arrays. In Proceedings of the 17th International Workshop on Languages and Compilers for Parallel Computing (LCPC 2004), September 2004.
- G. Pokam, F. Bodin. Understanding the Energy-Delay Tradeoff of ILP-based Compilation Techniques on a VLIW Architecture. In Proceedings of the 11th Workshop on Compilers for Parallel Computers (CPC 2004), July 2004.
- Gilles Pokam, Olivier Rochecouste, André Seznec, Francois Bodin. Speculative Software Management of Datapath-width for Energy Optimization. In proceedings of the Conference on Languages, Compilers, and Tools for Embedded Systems (LCTES'04), June 2004.
- Gilles Pokam, François Bodin. Exploring the energy-efficiency potential of a phase-based cache resizing scheme for embedded systems. In Proceedings of the 8th Annual Worskhop on Interaction between Compilers and Computer Architectures (INTERACT-8), February 2004.
- André Seznec. The O-GEHL branch predictor. In Proceedings of the First Workshop ChampionShip Branch Prediction in conjunction with MICRO-37, December 2004.
National Conferences
- I. Puaut, A. Arnaud, D. Decotigny. Analyse de performance de méthodes de verrouillage statique de caches dans les systèmes temps-réel strict. In Proc. of the 12th International Conference on Real-Time Systems (RTS'04), March 2004.
Research Reports
- Pierre Michaud. Analysis of a tag-based branch predictor. Research Report IRISA, No 0, November 2004.
- André Seznec. Revisiting the perceptron predictor. Research report IRISA, No 0, May 2004.
Thesis
- Amaury Darsch. L'exécution dans le désordre des jeux d'instructions prédiquées. PhD Thesis University of Rennes I, December 2004.
- Antony Fraboulet. Génération des adresses des instructions pour les processeurs superscalaires fortement pipelinés. PhD Thesis Université de Rennes I, December 2004.
- Karine Heydemann. Schéma de compilation global sous contraintes pour la recherche de compromis entre la taille d'un code et sa performance. PhD Thesis University of Rennes I, December 2004.
- Gilles Pokam. Techniques de compilation pour la gestion et l'optimisation de la consommation d'énergie des architectures VLIW. PhD Thesis University of Rennes I, July 2004.
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