Publications 2002
International Conferences
- Ronan Amicel, François Bodin. Mastering Startup Costs in Assembler-Based Compiled Instruction-Set Simulation. In 6$^th$ Annual Workshop on Interaction between Compilers and Computer Architectures (INTERACT-6), Cambridge, ƒtats-Unis, February 2002.
- R. Espasa, F. Ardanaz, J. Emer, S. Felix, J. Gago, R. Gramunt, I. Hernandez, T. Juan, G. Lowney, M. Mattina, A. Seznec. Tarantula: A Vector Extension to the Alpha Architecture. In Proceedings of the 29th International Symposium on Computer Architecture (IEEE-ACM), Anchorage, May 2002.
- Antoine Monsifrot, François Bodin. A Machine Learning Approach to Automatic Production of Compiler Heuristics. In Tenth International Conference on Artificial Intelligence: Methodology, Systems, Applications (AIMSA 2002), September 2002.
- I. Puaut. Real-Time Performance of Dynamic Memory Allocation Algorithms. In Proc. of the 14th Euromicro Conference on Real-Time Systems, Pages 41-49, Vienna, Austria, June 2002.
- I. Puaut. Cache Analysis vs Static Cache Locking for Schedulability Analysis in Multitasking Real-Time Systems. In Proc. of the 2nd International Workshop on worst-case execution time analysis, in conjunction with the 14th Euromicro Conference on Real-Time Systems, Vienna, Austria, June 2002.
- I. Puaut, D. Decotigny. Low-Complexity Algorithms for Static Cache Locking in Multitasking Hard Real-Time Systems. In Proc. of the 23rd IEEE International Real-Time Systems Symposium, Austin, TX, USA, December 2002.
- André Seznec, Steve Felix, Vishnan Krishnan, Yanos Sazeides. Design trade-offs on the EV8 branch predictor. In Proceedings of the 29th International Symposium on Computer Architecture (IEEE-ACM), Anchorage, May 2002.
- A. Seznec, E. Toullec, O. Rochecouste. Register Write Specialization Register Read Specialization: A Path to Complexity Effective of Wide Issue Superscalar Processors. In Proceedings of the 35th International Symposium on Microarchitecture (IEEE-ACM), Istamboul, November 2002.
- A. Seznec, N. Sendrier. HAVEGE: Hardware volative entropy gathering and expansion unpredictable random number generation at user level. In Workshop on Random Number Generators and Highly Uniform Point Sets, Montréal, June 2002.
Research Reports
- A. Colin, I. Puaut, C. Rochange, P. Sainrat. Calcul de majorants de pire temps d'exécution : état de l'art. Research Report IRISA, No 0, May 2002.
- Romain Dolbeau, André Seznec. CASH: Revisiting hardware sharing in single-chip parallel processor. Rapport de recherche IRISA, No 1491, October 2002.
- Pierre Michaud. A Statistical Study of Skewed Associativity. Rapport de recherche IRISA, No 1489, October 2002.
- I. Puaut. Real-time performance of dynamic memory allocation algorithms. Research Report IRISA, No 0, January 2002.
- André Seznec, Nicolas Sendrier. HArdware Volatile Entropy Gathering and Expansion: generating unpredictable random number at user level. Rapport de recherche IRISA, No 1492, October 2002.
Thesis
- Antoine Monsifrot. Utilisation du raisonnement ˆ partir de cas et de l'apprentissage pour l'optimisation de code. PhD Thesis, December 2002.
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