Publications 2001

Academic Journals

1. François Bodin, Antoine Monsifrot. Performance Issues in Automatic Differentiation on Superscalar Processors. Automatic Differentiation: From Simulation to Optimization, 2001.
2. Pierre Michaud, André Seznec, Stéphan Jourdan. An exploration of instruction fetch requirement in out-of-order superscalar processors. International Journal of Parallel Programming, February 2001.

International Conferences

1. A. Colin, I. Puaut. A modular and retargetable framework for tree-based WCET analysis. In Proc. of the 13th Euromicro Conference on Real-Time Systems, Pages 37-44, Delft, The Netherlands, June 2001.
2. A. Colin, I. Puaut. Worst-Case Execution Time Analysis of the RTEMS Real-Time Operating System. In Proc. of the 13th Euromicro Conference on Real-Time Systems, Pages 191-198, Delft, The Netherlands, June 2001.
3. Kun Luo, Manoj Franklin, Shubhendu S. Mukherjee, André Seznec. Boosting SMT Performance by Speculation Control. In International Parallel Processing Symposium, April 2001.
4. Pierre Michaud, André Seznec. Data-flow prescheduling for large instruction windows in out-of-order processors. In 7th International Conference on High Performance Computer Architecture, January 2001.
5. Pierre Michaud, André Seznec. Data-flow prescheduling for large instruction windows in out-of-order processors. In 7th International Conference on High Performance Computer Architecture, January 2001.
6. Antoine Monsifrot, François Bodin. Computer Aided Hand Tuning (CAHT): "Applying Case-Based Reasoning to Performance Tuning". In International Conference on Supercomputing, June 2001.

National Conferences

1. A. Colin, I. Puaut. Analyse de temps d'exécution au pire cas du système d'exploitation temps-réel RTEMS. In Seconde Conférence Française sur les Systèmes d'Exploitation (CFSE2), Pages 73-84, Paris, France, April 2001.

Research Reports

1. A. Colin, I. Puaut. A modular and retargetable framework for tree-based WCET analysis. Research Report IRISA, No 0, March 2001.
2. Karine Heydemann, François Bodin, Peter Knijnenburg. Global Trade-off between Code Size and Performance for Loop Unrolling on VLIW Architectures. publication interne Irisa, No 1390, 2001. download
3. Pierre Michaud, André Seznec. A Comprehensive Study of Dynamic Global History Branch Prediction. Rapport de recherche INRIA, No 4219, June 2001. download
4. André Seznec. A Path to Complexity-Effective Wide-Issue Superscalar Processors. Rapport de recherche INRIA, No 4242, August 2001. download

Misc

1. Laurent Bertaux, François Bodin. "ALISE : An Infrastructure for Assembly Level Tools", IFIP Working Group 2.4, Software Implementation Techniques, San Miniato, Italy, May 28 - June 1. 2001.

Thesis

1. I. Puaut. Supports d'exécution à temps de réponse contraint tolérants aux fautes. Habilitation à diriger des recherches Université de Rennes I, November 2001.

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