Publications of Andre Seznec

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Academic Journals

1. A. Seznec. Concurrent support of multiple page sizes on a skewed associative TLB. IEEE Transactions on Computers, July 2004.
2. Romain Dolbeau, André Seznec. CASH: Revisiting hardware sharing in single-chip parallel processor. Journal of Instruction Level Parallelism, April 2004.
3. A. Seznec, N. Sendrier. HAVEGE: a user-level software heuristic for generating empirically strong random numbers. ACM Transactions on Modeling and Computer Systems, October 2003.
4. Pierre Michaud, André Seznec, Stéphan Jourdan. An exploration of instruction fetch requirement in out-of-order superscalar processors. International Journal of Parallel Programming, February 2001.
5. Erven Rohou, François Bodin, Christine Eisenbeis, André Seznec. Handling Global Constraints in Compiler Strategy. International Journal of Parallel Programming, 2000.
6. T. Lafage, André Seznec Kluwer. Choosing Representative Slices of Program Execution for Microarchitecture Simulations: A Preliminary Application to the Data Stream. Workload Characterization, 0.
7. Pierre Michaud, André Seznec, Stéphan Jourdan. An exploration of instruction fetch requirement in out-of-order superscalar processors. International Journal of Parallel Programming, 0.
8. A. Seznec. Concurrent support of multiple page sizes on a skewed associative TLB. IEEE Transactions on Computers, 0.

International Conferences

1. André Seznec. The O-GEHL branch predictor. In Proceedings of the First Workshop ChampionShip Branch Prediction in conjunction with MICRO-37, December 2004.
2. Amaury Darsch, Andre Seznec. IATO: A Flexible EPIC Simulation Environment. In Proceedings of the 16th Symposium on Computer Architecture and High Performance Computing (SBAC-PAD 2004), October 2004.
3. Gilles Pokam, Olivier Rochecouste, André Seznec, Francois Bodin. Speculative Software Management of Datapath-width for Energy Optimization. In proceedings of the Conference on Languages, Compilers, and Tools for Embedded Systems (LCTES'04), June 2004.
4. Julio César Hern‡ndez, José Mar’a Sierra, André Seznec. The SAC Test: A New Randomness Test, with Some Applications to PRNG Analysis. In Proceedings of the International Conference Computational Science and Its Applications - ICCSA 2004, LNCS vol. 3043, Pages 960-967, April 2004.
5. Julio Cesar Hernandez, Pedro Isasi, André Seznec. On the design of state-of-the-art pseudorandom number generators by means of genetic programming. In Proceedings of the 2004 IEEE Congress on Evolutionary Computation, Pages 1510-1516, Portland, Oregon, 2004.
6. André Seznec, Antony Fraboulet. Effective ahead pipelining of instruction block address generation. In Proceedings of the 30th Annual International Symposium on Computer Architecture (ISCA-03), Pages 241-252, 2003.
7. Assia Djabelkhir, André Seznec. Characterization of embedded applications for decoupled processor architecture. In Proceedings of the IEEE 6th Annual Workshop on Workload Characterization, Austin, TX, 2003.
8. A. Seznec, E. Toullec, O. Rochecouste. Register Write Specialization Register Read Specialization: A Path to Complexity Effective of Wide Issue Superscalar Processors. In Proceedings of the 35th International Symposium on Microarchitecture (IEEE-ACM), Istamboul, November 2002.
9. A. Seznec, N. Sendrier. HAVEGE: Hardware volative entropy gathering and expansion unpredictable random number generation at user level. In Workshop on Random Number Generators and Highly Uniform Point Sets, Montréal, June 2002.
10. André Seznec, Steve Felix, Vishnan Krishnan, Yanos Sazeides. Design trade-offs on the EV8 branch predictor. In Proceedings of the 29th International Symposium on Computer Architecture (IEEE-ACM), Anchorage, May 2002.
11. R. Espasa, F. Ardanaz, J. Emer, S. Felix, J. Gago, R. Gramunt, I. Hernandez, T. Juan, G. Lowney, M. Mattina, A. Seznec. Tarantula: A Vector Extension to the Alpha Architecture. In Proceedings of the 29th International Symposium on Computer Architecture (IEEE-ACM), Anchorage, May 2002.
12. Kun Luo, Manoj Franklin, Shubhendu S. Mukherjee, André Seznec. Boosting SMT Performance by Speculation Control. In International Parallel Processing Symposium, April 2001.
13. Pierre Michaud, André Seznec. Data-flow prescheduling for large instruction windows in out-of-order processors. In 7th International Conference on High Performance Computer Architecture, January 2001.
14. Pierre Michaud, André Seznec. Data-flow prescheduling for large instruction windows in out-of-order processors. In 7th International Conference on High Performance Computer Architecture, January 2001.
15. T. Lafage, André Seznec. Choosing Representative Slices of Program Execution for Microarchitecture Simulations: A Preliminary Application to the Data Stream. In Workshop on Workload Characterization (WWC 2000), September 2000.
16. T. Lafage, A. Seznec. Combining Light Static Code Annotation and Instruction-Set Emulation for Flexible and Efficient On-the-fly Simulation. In Euro-Par 2000, Munich, August 2000.

Research Reports

1. André Seznec. Revisiting the perceptron predictor. Research report IRISA, No 0, May 2004.
2. Amaury Darsch, André Seznec. Out-of-order execution of predicated instruction sets through translation register buffers. Research Report IRISA, No 1573, November 2003. download
3. André Seznec. Redundant History Skewed Perceptron Predictors: pushing limits on global history branch predictors. Research report IRISA, No 1554, September 2003.
4. André Seznec, Nicolas Sendrier. HArdware Volatile Entropy Gathering and Expansion: generating unpredictable random number at user level. Rapport de recherche IRISA, No 1492, October 2002.
5. Romain Dolbeau, André Seznec. CASH: Revisiting hardware sharing in single-chip parallel processor. Rapport de recherche IRISA, No 1491, October 2002.
6. André Seznec. A Path to Complexity-Effective Wide-Issue Superscalar Processors. Rapport de recherche INRIA, No 4242, August 2001. download
7. Pierre Michaud, André Seznec. A Comprehensive Study of Dynamic Global History Branch Prediction. Rapport de recherche INRIA, No 4219, June 2001. download

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