- got his Ph.D. with the CAPS group in October 2005 -


Contact information

Campus de Beaulieu
35042 RENNES Cedex

phone: +33 2 99 84 25 61

e-mail: orocheco@irisa.fr

Current position

From September 2006 to September 2007, I will assume a position of temporary teaching and research associate (ATER) at University of Rennes I.

Research interests

My current research interest is in the area of computer architecture with a main emphasis on:

  • Complexity-effective microarchitectures
  • Power-aware designs
  • High-performance systems
  • Cooperative hardware/software optimizations
  • Clustered processor organization
  • Multicore processors

Ph.D. thesis

I successfully defended my Ph.D. thesis on October 24th, 2005. It has been supervised by André Seznec since October 2001. Both the thesis manuscript and the presentation slides are available for download in french only.


Mastering both hardware complexity and power consumption has become essential in modern processor design. In this thesis, we address these issues by means of two novel techniques. Central to our proposals is the observation that program executions are comprised of a large amount of narrow-width data. First, we suggest to use this property to manage the power consumption of the processor datapath at the software level. Our approach consists in exploiting the bitwidth locality available in programs to speculatively tailor the processor datapath-width to the execution needs. Second, we show that narrow-width operations, i.e. operations exclusively handling narrow-width data, are prevalent and well distributed across a program run. We advocate using a Width-Partitioned Microarchitecture (WPM) to decouple the treatment of these narrow-width operations on a dedicated datapath-width. In our study, we only examine simple configurations of WPM but yet very effective to reduce the complexity with reasonable impacts on performance.

Professional Experience

From December 2005 to September 2006, I assumed a position of research engineer at IRISA within the CAPS group.

I was mainly concerned with the software development and packaging of HAVEGE: an unpredictable hardware random generator proposed by André Seznec and Nicolas Sendrier, described there.

HAVEGE is now released under the terms of GNU LGPL. HAVEGE is available as a kernel module for Linux systems and as a shared & static libraries for Linux and Windows environments.


    Ph.D. thesis

  • Architecture et bits significatifs. [pdf][ps][presentation slides]
    Olivier Rochecouste. Ph.D. Thesis, #3092, University of Rennes 1, France, October 2005.
  • Journal Articles

  • A Case for a Complexity-Effective, Width-Partitioned Microarchitecture. [ACM link]
    Olivier Rochecouste and Gilles Pokam and André Seznec. ACM Transactions on Architecture and Code Optimisation (TACO), Volume 3 , Issue 3, September 2006.
  • Conference Papers

  • Speculative Software Management of Datapath-width for Energy Optimization. [pdf]
    Gilles Pokam and Olivier Rochecouste and André Seznec and François Bodin. In Proceedings of the ACM SIGPLAN/SIGBED 2004 Conference on Language, Compiler, and Tool for Embedded Systems (LCTES'04). Washinghton DC, June 2004.
  • Register Write Specialization Register Read Specialization: A Path to Complexity-Effective Wide Issue Superscalar Processors. [pdf]
    André Seznec and Eric Toullec and Olivier Rochecouste. In Proceedings of the 35th International Symposium on Microarchitecture (IEEE-ACM) (MICRO-35). Istanbul, November 2002.
  • Research Reports

  • A Case for a Complexity-Effective, Width-Partitioned Microarchitecture. [link]
    Olivier Rochecouste and Gilles Pokam and André Seznec. INRIA Research Report, RR-5677, September 2005.
Note: contact me if you encounter problems downloading any of the links above.