Back to school. I am currently a PhD student in the
CAPS team at IRISA, and my advisor is André Seznec. The title
of my PhD thesis is "Out-of-order execution with predicated ISA".
Several new generation processors make extensive
use of predication and large register file. Unlike traditional ISA, these
new instruction sets are resistant to an out-of-order architecture, because
of the resource size as well as the complexity of executing predicated instructions.
Although, the research community has started to study the execution of predicated
instruction within an out-of-order core, no definitive solution has been
adopted yet. The current research activity is primarily focused in determining
new architectures that permit to execute fully predicate ISA within an out-of-order
core and still maintaining a high IPC.
As part of the research activity, a complex simulation environment for the
IA64 platform as been developed. The project is called IATO and is
freely to the research community.
September 1998, September 2001
Cadence Design System, San Jose, Ca, USA.
February 1997, September 1998
Aristo Technology Inc, Cupertino, Ca,
June 1995, February 1997
Compass Design Automation Inc, San Jose,
March 1993, June 1995
Compass Design Automation Inc, Paris,
June 1989, March 1993
VLSI Technology, Sophia Antipolis, France.
Campus de Beaulieu
35042 RENNES Cedex