contact information

IRISA
Campus de Beaulieu
35042 RENNES Cedex
FRANCE

phone: +33 2 99 84 75 37
fax: +33 2 99 84 25 28

e-mail: sbihan@irisa.fr

Expert engineer in the CAPS team from June 2001 to November 2003, I am now working as chief of the engineering operations in the CAPS entreprise start-up since January 2004.

CAPS entreprise industrializes a set of frameworks developped in the CAPS team which facilitates the implementation of code optimizers and simulators and offers its customers software tools and services that improve code quality of their embedded and high performance system applications.

CAPS activities

Part of the MESA project from the Medea+ European Program, we have developped a reconfigurable C to C preprocessor that exploits multimedia instructions.

Multimedia Instructions have been introduced to fullfill the requirements of computation-intensive multimedia applications. These instructions (SIMD instructions) operate on a set of data packed into one machine register. For instance typical video applications use 8-bit data while audio applications may use 16-bit data.

Our C preprocessor is able to exhibit parallel sections of code by using code transormations such as loop unrolling, loop distribution and vectorization. Code transformations for using multimedia instructions are driven by a set of rules. These rules are described using C patterns.

We also worked on a Distributed Compilation system that enabled authorized user to access remote tools as if they were installed on site. This system is based on a client-server system.

Previous activities

Prior to working at IRISA, I was research engineer at Canon Research Centre France, in Rennes. Our activity was to find new solutions in the design of real time embedded applications in order to take maximum profit of the hardware.

I also worked one and an half year at ARC Cores plc in London as software engineer. ARC Cores provides a 32-bit user configurable processor with a suite of tools for configuration and hardware/software co-design, to design complete embedded SoCs. I worked in the software tools departement, in charge of providing configurable development tools such as compilers, debuggers and simulators. I have designed DLLs that allow the debuggers to access the ARC processor in its hardware form (FPGA) or sofware form (simulator). I also extended the GNU gdb debugger to support the configurable ARC processor.

Background

Post graduate engineering degree, IFSIC, Rennes.

6 month student project in CAPS: writing an advanced profiling algorithm for Salto.

6 month training at ACE, Amsterdam, The Netherlands: prototyping a CoSy compiler back-end for the VLIW TMS320C6xx.