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Fault-Tolerant Reconfigurable Systems
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The use of reconfigurable hardware in critical applications like transportation and transaction systems is increasing rapidly. Undetected errors caused e.g. by radiation may result in fatal silent data corruption and unreproducible system crashes. Since it is virtually impossible to build devices which are free from faults, it is essential to embed some sort of fault-tolerance in such devices, which will enable them to work correctly even in the presence of faults. Since the past decade, a lot of research has been done to develop fault-tolerant reconfigurable systems on various granularity levels, although most of them have dealt with the lowest level such as offered by FPGAs.
We have considered the possibility of implementing low-cost hardware techniques which would allow to tolerate temporary faults in the data-paths of coarse-grained reconfigurable architectures. Our goal was to use less hardware overhead than commonly used duplication or triplication methods. The proposed technique relies on concurrent error detection by using residue code modulo 3 and re-execution of the last operation, once an error is detected. Simulation results performed for the DART architecture developed at IRISA with all of its data-paths protected using residue code confirmed hardware savings of the proposed approach over duplication.
To cope with the high sensitivity of electronic devices to failures or soft errors, we also proposed a multiprocessor system on an dynamically reconfigurable architecture for the design of fault-tolerant systems. First we have proposed and designed a flexible communication model which ensures reliable communication. This work accomplished in the CIFAER (in french) project permits to switch from a communication protocol, by reconfiguring the reserved zone for the communication protocol, to a secondary one in order to mitigate communication errors. Some possibilities to integrate this dynamic platform into standardized automotive software infrastructure have also been introduced.
In order to exploit the computational power and the flexibility of reconfigurable architecture, and at the same time to guarantee the correct functionality of the entire system, we proposed a fully dynamic MPSoC topology. In this system, all the processors can be dynamically reconfigured, moved or replaced in the system, hence providing fault-tolerant and self-repair capability. A deep exploration of a standard design flow has been done to facilitate the design of this architecture using commercially available FPGAs.
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