Management of Dynamically Reconfigurable Systems

To support the dynamic behavior of new embedded applications, heterogeneous execution resources are often included in modern SoC or MPSoC (Multi-Processor System-on-Chip) systems. The management of this resource is classically supported by an operating system (OS) that includes several specific services. One new needed service concerns the task scheduling and placement within the reconfigurable resources. The classical temporal scheduling problem is then extended with a spatial dimension in order to manage the physical available area into the reconfigurable resource. The second impacted service is the task communication management. The on-line task placement makes the interconnection support difficult to predict. Then, a flexible and dynamically interconnect medium must be defined.

•  Models for Dynamically Reconfigurable Systems

During the high level design of the complete system, the designer must be able to choose between different architecture, application and operating system solutions. To support the exploration phase, the OverSoC project has proposed to develop a global methodology. In this context, we developed a first model of a dynamically reconfigurable architecture (DRA). Built using SystemC language, the model is modular and permits the fast evaluation of specific OS services for DRA management. Based on this model, we implemented several services, such as a simple task placement, and evaluated several design parameters to qualify solutions. The model is effective and was integrated in the OverSoC methodology.

•  Scheduling based on Artificial Neural Networks

During this year, we continued our work on scheduling through Artificial Neural Networks (ANN) and we compared classical scheduling algorithms (e.g. PFair) and our ANN structure composed of inhibitor neurons. We have demonstrated that our model can manage heterogeneous multiprocessor architectures while classical scheduling solutions are only applicable for homogeneous multiprocessors. Our scheduling was extended with task placement on heterogeneous reconfigurable execution resource by defining a spatio-temporal scheduling composed of two steps. The first step is the time scheduling under a resource placement constraint. The second step is the task placement with a real model of the possible instances of each application task. These two steps are solved by two different neural networks which can be evaluated in parallel.
A hardware structure of our neural network has been developed for the temporal scheduler and shows that hardware implementation is very efficient and can be a very good candidate for hardware implementation of this service.

• Flexible Communication Infrastructure

For task communication within the reconfigurable resource, we defined a specific interconnection architecture adapted to dynamically and partially reconfiguration resources included into modern SoC and proposed structures which are well-suited for state-of-the-art dynamically reconfigurable chips. We defined a first hierarchical interconnect infrastructure and specified an RTL VHDL model of this solution. Furthermore, to evaluate our architectural proposal, we built a demonstrator platform which allows us to illustrate the reconfiguration concept of the communication network. This leads to the DRAFT network based on the fat-tree topology, specifically designed to support the communication constraints required by the dynamic reconfiguration. DRAGOON, an automatic generator of DRAFT simulation and synthesis models, was also designed to evaluate various versions of the network. Thanks to DRAGOON, DRAFT has successfully been compared with most popular Network-on-Chip (NoC) topologies, like mesh and regular fat-tree.