PhD
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Design and performance evaluation of an energy-efficient 3D heterogeneous multicore with on-chip optical interconnect
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Performance evaluation and optimization of fixed-point systems
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Evaluation des performances et optimisation de systèmes en virgule fixe
- Thèse CIFRE en collaboration avec ST Microelectronics : Evaluation des performances et optimisation de systèmes en virgule fixe
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Power Aware Signal Processing for Reconfigurable Radios in the context of Wireless Sensor Networks
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A Self-Healing Reconfigurable Accelerator Structure for Fault-Tolerant Multi-Cores in Embedded Applications
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Performances evaluation in fixed-point arithmetic
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Global power management system for self-powered autonomous wireless sensor node
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Sampling, synchronising, digital processing and FPGA implementation of 100Gbps optical OFDM signals
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Performance/Accuracy Trade-off in Automatic Parallelization for SIMD Hardware Accelerators
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3D-stacked hardware accelerators with virtualized dynamic reconfiguration in a heterogeneoous multicore
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document.2011-07-29.7399898558