Ochre V1 Circuit : On-Chip Randomness Extraction

Document Actions

Characteristics

Technology: CMOS 130 nm, STMicroelectronics HCMOS9GP
Size: 1 mm²
Fabrication: CMP facilities (run January 2009)
Tools: front end: Synopsys Design Complier for synthesis and Mentor-Graphics ModelSim for simulation
back end: Cadence Encounter for place&route, Mentor-Graphics Calibre for Verification and Cadence Virtuoso for tape-out
(tools provided by CNFM)
Validation: Fully operational
Designers: Renaud Santoro, Philippe Quémerais, Thomas Anger
Contact: Olivier Sentieys

Description

The number of hardware applications requiring a hardware Random Number Generator (RNG) is continuously increasing, specially in embedded circuits (e.g. Field Programmable Gate Array (FPGA) or System-on-Chip). As a consequence, many applications need an embedded RNG with the highest quality and security level. The OCHRE V1 chip implements a hybrid RNG composed of a True Random Number Generator (TRNG) and a Pseudo Random Number Generator (PRNG). The TRNG randomness quality is monitored on real-time by hardware statistical tests. As a result, the design is able to detect TRNG weaknesses due to defects or to non-invasive attacks.