Accès à l'intranet
Français
Views
- State: published
English
Automatic mapping of RVC application to TTA-based processors network
Document Actions
The increasingly demanding requirements for multimedia applications lead to more and more complex algorithms and systems to be implemented. To handle this increase in complexity and the "time to market" pressure, new video coding standards and automated design processes are required. Reconfigurable Video Coding (RVC) standard allows defining new codec algorithms based on a modular library of components. Flexibility and reconfigurability are targeted. The dataflow-based specification formalism enables to automate the mapping on both software and hardware components of a SoC-based platform.
The Transport Triggered Architecture (TTA) is a kind of CPU design in which programs directly control the internal transport buses of a processor. Computation happens as a side effect of data transports: writing data into a triggering port of a functional unit triggers the functional unit to start computation. This is close to the behavior of dataflow architecture. Due to its modular structure, TTA is an ideal processor template for application-specific instruction-set processors (ASIP) with customized datapath but without the inflexibility and design cost of fixed function hardware accelerators.
In this talk, we will present a way to join these two concepts using a framework that maps RVC applications to a network of TTA-based processors which communicate by FIFO channels.
- What
- Meeting
- When
-
08.12.2011
from
15:00
to
16:00
- Where
- ENSSAT- 020G
- Name
- Sébastien Pillement
- Contact Email
- pillemen@irisa.fr
Gecos: a source-to-source compiler for high-level synthesis