Defying Amdahl’s Law - DAL

André Seznec

04-2011/03-2016

In 2010, André Seznec has been awarded an ERC advanced grant,  for the DAL proposal. This project will span from 04-2011 to 03-2016

Proposal summary

DAL participants

Joining DAL

DAL related publications

Proposal summary (Full proposition, pdf version)

Multicore processors have now become mainstream for both general-purpose and embedded computing. Instead of working on improving the architecture of the next generation multicore, with the DAL project, we deliberately anticipate the next few generations of multicores.

While multicores featuring 1000’s of cores might become feasible around 2020, there are strong indications that sequential programming style will continue to be dominant. Even future mainstream parallel applications will exhibit large sequential sections. Amdahl’s law indicates that high performance on these sequential sections is needed to enable overall high performance on the whole application. On many (most) applications, the effective performance of future computer systems using a 1000-core processor chip will significantly depend on their performance on both sequential code sections and single thread.

We envision that, around 2020, the processor chips will feature a few complex cores and many (may be 1000’s) simpler, more silicon and power effective cores.

In the DAL research project, we will explore the microarchitecture techniques that will be needed to enable high performance on such heterogeneous processor chips. Very high performance will be required on both sequential sections -legacy sequential codes, sequential sections of parallel applications- and critical threads on parallel applications -e.g. the main thread controlling the application. Our research will focus on enhancing single process performance. On the microarchitecture side, we will explore both a radically new approach, the sequential accelerator, and more conventional processor architectures. We will also study how to exploit heterogeneous multicore architectures to enhance sequential thread performance.

DAL participants

• André Seznec, principal investigator,
• Pierre Michaud,  researcher,
• Erven Rohou, researcher,
• Bharat N Swany,  PhD student, joined Sep 2011,  Exploiting heterogeneous manycores on sequential code
• Luis German Garcia Morales, PhD student, joined Oct 2011, Sequential Accelerators in Future Manycore Processors
• Surya Natarajan, PhD student, joined january 2012,  What makes parallel code sections and sequential code sections different?
• Ricardo Velasquez, PhD student,
  
• Nathanael Premillieu, PhD student.
• Kamil Kedzierski, Postdoc, joined january 2012, Performance, Power and Reliability Constraints for Sequential Accelerators in Future Manycore Processors

Want to join the ALF team to work on the DAL project ?

DAL is offering several PhD fellowships as well as several postdoc fellowships.

As an intern:

• We will hire master research interns, summer interns etc on this project, just contact This e-mail address is being protected from spambots. You need JavaScript enabled to view it

As a PhD candidate:

• contact This e-mail address is being protected from spambots. You need JavaScript enabled to view it
• Indicative list of  PhD topics:

  • Sequential Accelerators in Future Manycore Processors

  • Exploiting heterogeneous manycores on sequential code

  • What makes parallel code sections and sequential code sections different?
  • Still open: Improving single core execution in the many-core era

As a postdoc:

• 2 two-years postdoc research positions are open, contact This e-mail address is being protected from spambots. You need JavaScript enabled to view it
• Postdoc researchers are expected to exhibit a large autonomy in their research. They will have to define their research program in collaboration with André Seznec and the researchers in the DAL project.
• Indicative list of postdoc topics:

  • Sequential Accelerators in Future Manycore Processors

  • still open:    Ultimate Single Core Microarchitecture
  • still open:    Exploiting heterogeneous manycores on sequential code

DAL related publications

A. Seznec  "A 64 Kbytes ISL-TAGE branch predictor", winner of the 3rd Championship Branch Prediction, conditional branch track, JWAC-2, june 2011, in cunjounction with ISCA 2011.

A. Seznec  "A 64 Kbytes ITTAGE branch predictor", winner of the 3rd Championship Branch Prediction, indirect branch track,  JWAC-2, june 2011, in cunjounction with ISCA 2011.

A. Seznec, "A new case for the TAGE branch predictor", Proceedings of the 44th International Symposium on Microarchitecture (ACM-IEEE), Porto Allegre, december 2011.

H. Vandierendonck, A. Seznec, "Managing SMT Resource Usage through Speculative Instruction Window Weighting", ACM Transactions on Computer Architecture, October 2011.