Damien Hardy

Contact information

IRISA, ALF Research Group
Postal address: IRISA Campus universitaire de Beaulieu 35042 Rennes Cedex FRANCE
E-mail address: This e-mail address is being protected from spambots. You need JavaScript enabled to view it
Room: E-318
Telephone: +33 2 99 84 25 51
Fax number: +33 2 99 84 71 71

Current position

Temporary teaching and research associate (ATER) at University of Rennes I

PhD thesis

I successfully defended my PhD thesis (PhD thesis(fr) and presentation(fr)) on December 9th, 2010. It has been supervised by Isabelle Puaut since October 2007.

Research interests

• Hard real-time systems, worst-case execution time (WCET)
• Timing predictability of embedded software on multicore architectures
• Timing analysis of cache hierarchy
• Compiler-decided management of virtual memory

Activities

• PC member of JRWRTC 2011 (Junior Researcher Workshop on Real-Time Computing).
• PC member of JRWRTC 2010 (Junior Researcher Workshop on Real-Time Computing).
• PC member of RTSS2008 Work-in-Progress Session (Real-Time Systems Symposium).

Teaching resources

• L3 SEA (Systèmes embarqués dans l'automobile)
  • OSEK/VDX practicals repository. See also Trampoline, the OSEK/VDX compliant open source real-time operating system (RTOS). See also Slax, a sligtly modified version is distributed to students for practicals.
• Master1
  • Compilers: laboratory work using ANTLR v2. See also the documentation and repository.

Publications

Academic Journals

D. Hardy, I. Puaut. WCET analysis of instruction cache hierarchies. Journal of Systems Architecture, 2010 To appear.

International Conferences

B. Lesage, D. Hardy, I. Puaut. Shared Data Cache Conflicts Reduction for WCET Computation in Multi-Core Architectures. In Proc. of the 18th Real-Time and Network Systems, Toulouse, France, November 2010.

D. Hardy, T. Piquet, I. Puaut. Using Bypass to Tighten WCET Estimates for Multi-Core Processors with Shared Instruction Caches. In Proc. of the 30th IEEE Real-Time Systems Symposium, Washington D.C., USA, December 2009.

D. Hardy, I. Puaut. Estimation of Cache Related Migration Delays for Multi-Core Processors with Shared Instruction Caches. In Proc. of the 17th Real-Time and Network Systems, Paris, France, October 2009.

D. Hardy, I. Puaut. WCET analysis of multi-level non-inclusive set-associative instruction caches. In Proc. of the 29th IEEE Real-Time Systems Symposium, Barcelona, Spain, December 2008.

D. Hardy, I. Puaut. Predictable code and data paging for real-time systems. In Proc. of the 20th Euromicro Conference on Real-Time Systems, Prague, Czech Republic, July 2008.

I. Puaut, D. Hardy. Predictable paging in real-time systems: a compiler approach. In Proc. of the 19th Euromicro Conference on Real-Time Systems, Pisa, Italy, July 2007.

Workshop/Research Report

B. Lesage, D. Hardy, I. Puaut. WCET analysis of multi-level set-associative data caches. 9th Int'l Workshop on Worst-Case Execution Time Analisis (WCET 2009), Dublin, Ireland, July 2009.

D. Hardy, T. Piquet, I. Puaut. Using Bypass to Tighten WCET Estimates for Multi-Core Processors with Shared Instruction Caches. Research Report IRISA, No 6907, April 2009.

A. Junier, D. Hardy, I. Puaut. Impact of instruction cache replacement policy on the tightness of WCET estimation. 2nd Junior Researcher Workshop on Real-Time Computing (JRWRTC 2008), Rennes, France, Oct 2008.

D. Hardy, I. Puaut. WCET analysis of multi-level set-associative instruction caches. Research Report IRISA, No 6574, June 2008.

D. Hardy, I. Puaut. Predictable paging in real-time systems: an ILP formulation. Ecole d'été Temps Réel (ETR'07), Nantes, France, Sep 2007.

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