Contact information

INRIA
Campus de Beaulieu
35042 RENNES Cedex
FRANCE

e-mail: This e-mail address is being protected from spambots. You need JavaScript enabled to view it

About me

I am Chargé de Recherche at INRIA in Rennes in the ALF team. My research area is microarchitecture and related problems like microarchitecture simulation.

Papers

• R. A. Velásquez, P. Michaud, A. Seznec,"Selecting benchmark combinations for the evaluation of multicore throughput", International Symposium on Performance Analysis of Systems and Software, April 2013.

• P. Michaud, "Constant-work multiprogram throughput metrics for microarchitecture studies", INRIA report RR-8150, November 2012.

• P. Michaud, "Demystifying multicore throughput metrics", IEEE Computer Architecture Letters, 2012.

• R. A. Velásquez, P. Michaud, A. Seznec, "BADCO: Behavioral application-dependent superscalar core model", 12th International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS), 2012.

• P. Michaud, "Hardware acceleration of sequential loops", INRIA report RR-7802, November 2011.
  

• P. Michaud, "Replacement policies for shared caches on symmetric multicores : a programmer-centric point of view", 6th International Conference on High-Performance and Embedded Architectures and Compilers, January 2011. Technical report. Slides.

• P. Michaud, "The 3P and 4P cache replacement policies", 1st JILP Workshop on Computer Architecture Competitions (JWAC-1), Cache Replacement Championship, June 2010. Slides. Code.

• P. Michaud, Y. Sazeides, A. Seznec, "Proposition for a sequential accelerator in future general-purpose manycore processors and the problem of migration-induced cache misses", ACM International Conference on Computing Frontiers, May 2010.

• P. Michaud, "Online compression of cache-filtered address traces", IEEE International Symposium on Performance Analysis of Systems and Software, April 2009. slides. (ATC Software).

• P. Michaud, "Periodic activity migration for fast sequential execution in future heterogeneous multicore processors", November 2008, INRIA report RR-6735.

• P. Michaud, Y. Sazeides, A. Seznec, T. Constantinou, D. Fetis, "A study of thread migration in temperature-constrained multicores", ACM Transactions on Architecture and Code Optimization, Volume 4, Issue 2, June 2007.

• P. Michaud, Y. Sazeides, "ATMI: Analytical Model of Temperature in Microprocessors", Third Annual Workshop on Modeling, Benchmarking and Simulation (MoBS), June 2007. slides.

• P. Michaud, Y. Sazeides, "Scheduling issues on thermally constrained processors", October 2006, IRISA report PI-1822 and INRIA report RR-6006.

• D. Fetis, P. Michaud, "An evaluation of HotSpot-3.0 block-based temperature model", 5th Annual Workshop on Duplicating, Deconstructing, and Debunking, June 18, 2006. slides.

• A. Seznec, P. Michaud, "A case for (partially) tagged geometric history length branch prediction", Journal of Instruction Level Parallelism, Feb. 2006.

• P. Michaud, Y. Sazeides, A. Seznec, T. Constantinou, D. Fetis, "An analytical model of temperature in microprocessors", November 2005, IRISA report PI-1760 and INRIA report RR-5744

• T. Constantinou, Y. Sazeides, P. Michaud, D. Fetis, A. Seznec, "Performance Implications of Single Thread Migration on a Chip Multi-Core", ACM SIGARCH Computer Architecture News, volume 33, issue 4, November 2005.

• P. Michaud. "A PPM-like ,Tag-Based Branch Predictor", Journal of ILP, Vol. 7, 2005

• P. Michaud, "Analysis of a tag-based branch predictor", IRISA report PI-1660, November 2004 (also INRIA report RR-5366)

• P. Michaud, ``Exploiting the Cache Capacity of a Single-Chip Multi-Core Processor with Execution Migration'', 10th International Symposium on High Performance Computer Architecture, February 2004. ps, slides

• P. Michaud, ``A Statistical Model of Skewed Associativity'', International Symposium on Performance Analysis of Systems and Software, March 2003. slides

• P. Michaud, `` A Statistical Model of Skewed Associativity'', IRISA report PI-1489, October 2002 (also INRIA report RR-4582)

• P. Michaud, A. Seznec, `` A Comprehensive Study of Dynamic Global History Branch Prediction'', IRISA report PI-1406, June 2001 (also INRIA report RR-4219)

• P. Michaud, A. Seznec, S. Jourdan, ``An exploration of instruction fetch requirement in out-of-order superscalar processors'', International Journal of Parallel Programming, Vol.29 No.1, February 2001. ps

• P. Michaud, A. Seznec, ``Data-Flow Prescheduling for Large Instructions Windows in Out-of-Order Processors'', 7th International Symposium on High Performance Computer Architecture, January 2001. ps, slides

• P. Michaud, A. Seznec, S. Jourdan, ``Exploring Instruction-Fetch Bandwidth Requirement in Wide-Issue Superscalar Processors'', International Conference on Parallel Architectures and Compilation Techniques, October 1999.

• P. Michaud, "Chargement des instructions sur les processeurs superscalaires", PhD thesis (in french), November 1998.

• P. Michaud, A. Seznec, S. Jourdan, P. Sainrat, ``Alternative Schemes for High-Bandwidth Instruction Fetching'', IRISA Report 1180, March 1998.

• P. Michaud, A. Seznec, R. Uhlig, ``Trading Conflict and Capacity Aliasing in Conditional Branch Predictors'', Proceedings of the 24th International Symposium on Computer Architecture, June 1997. slides
  

• A. Seznec, S. Jourdan, P. Sainrat, P. Michaud, ``Multiple-Block Ahead Branch Predictors'', Proceedings of the 7th Conference on Architectural Support for Programming Languages and Operating Systems, October 1996.

Software

• ATMI - microprocessor temperature model

• STiMuL - steady temperature in multi-layers

• ATC - address trace compressor

Course (in French)

• Introduction à l'architecture des microprocesseurs

Miscellaneous

• Understanding the numbers that you get from your temperature model

• (Yet another) proof of optimality for MIN replacement

• The square-root law of instruction-level parallelism