CAPS

Compiler and architecture for superscalar and embedded processors

Context and objectives

IRISA joint project-team with INRIA, CNRS, INSA of Rennes, University of Rennes 1

The CAPS research team is working on architecture and compiler optimizations for building high performance microprocessor systems.

The theoretical performance of processors has been continously increasing for the past two decades. As several levels of parallelism are leveraged by the hardware, getting effective performance from applications requires software to concurrently exercise all these levels.

Research in the CAPS team aims at allowing the end user to exploit a significant fraction of this theoretical performance.

Research axes

• Architecture: We have proposed several new complexity-effective cache and branch predictor structures. Our current research effort aims at reducing the hardware costs of implementing wide-issue superscalar processors while continuing ongoing research on SMT architectures.
• Compilation: To achieve high performance on a processor, both ILP (instruction-level parallelism) and memory hierarchy must be correctly handled by the software.

  We study software optimization techniques to detect and exploit the locality of memory accesses. Scheduling techniques (software pipeline, loop unrolling, ...) are developped to expose more ILP to the hardware. These techniques are applied both to general-purpose processors and to embedded processors (e.g. media processors).

• Development environnements: The user has neither to be aware of the overall hardware complexity of processors, nor the software complexity of performance optimization. In order to hide these complexities to the user, specific development environments dedicated to performance are required. A significant part of our activity is dedicated to the definition and development of such environments.

International and industrial partnerships

Research on processor architecture and compilers in the CAPS team is partially supported by STMicroelectronics, Thomson multimedia and Intel.

The CAPS team is involved in the MESA MEDEA+ project in collaboration with STMicroelectronics and in the HIPSOR INRIA ARC project in collaboration with the CODES team from INRIA Rocquencourt.

Scientific leader

André Seznec
+33 2 99 84 73 36
Administrative assistant +33 2 99 84 73 34

About team

Web site

Software

HAVEGE

Topic

Communicating systems

All projects on this topic

Address

IRISA - Campus universitaire de Beaulieu - 35042 Rennes Cedex

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