This diagram is used to visualize/specify the interface of a Signal component (basically a process) or those of the declaration of a type used to type a component. The root of this diagram is a Model Declaration object, if you create it through the SME wizard, and can be either a Model Declaration or a Model Type otherwise. This diagram is used to specify the Input/Output signals and the constant Parameter of the interface of a component, and also some pragmas.
Each model elements that can have an Interface Definition Diagram contains a Specification model, whose role is to specify the clock relation between the input/output signals. If you want to modify or display it, drag it from the Outline view. This model is mainly used in component abstractions for separated compilation purposes.
To parametrize each of these elements, right-click on any graphical object and select the Property View. For more information, refers to the Parametrization of model objects section (select the Advanced tab, to view the attribute and references of each model object).