The compilation scenarios plug-in
The goal of this plug-in is to allow the creation of compilation scenarios for Polychrony model. A compilation scenario
is a sequence composed of different kinds of functionalities and of generators. A functionality modifies the internal representation
of the program whereas a generator translates this representation into a specific external format. The meta-model of this plug-in is
shown on the next picture.
Functionalities
For the moment, there are 9 different functionalities, which are those used in the current Polychrony graphical tool:
- Re-timing: It performs a shift register transformation. It rewrites synchronous function f such that Y :=
f(X1 $ m1 init V1,...,Xn $ mn init Vm) into Y := y' $ j init f(V1',...,Vm') and y' := f(X1 $ m1' init V1",...., Xm $ mn'
init Vm").
- Booleans to events: It rewrites boolean expressions of under-sampling for logical and relational operators. The goal is to
prove synchronization constraints of the system.
- the rewriting of the booleans expressions referenced in an extraction (when E) when E is not a "free"
condition and not declared as an assumption. For example, the expression when (A and B) is equal to the clock intersection
of when (A) and when (B).
So, "classical boolean rules" completed with some specific rules induced by
the extraction and merging Signal operators are applied to the system.
- the rewriting of the boolean expressions referenced in the extraction (when E) when E is assumed to be an assertion: the
expression assert(E) specifies that E is always true when it is available. So it induces that when E is equivalent to
the clock of E.
- Signal unifications: this operation consists in the merge of nodes into one node when their definition expression are equal
(syntactically).
- Clock calculus: it performs the resolution of the clock systems using a triangularization technique. A BDD-based data structure
is used. Here, only the study of static properties is performed. They allow to characterized the set of states in which the automaton
associated to a program can evolve, independently of initial values, and the set of the transitions between these states. The result
is a forest of clock trees.
- Events to booleans (bDC+): it performs the inter-format DC+ (that constrains event objects, forest of trees of clocks) to bDC+
(without event objects, a tree of boolean clock) translation.
- Abstraction: it computes the abstraction of the program (I/O data dependences, I/O clock relations, the "black Box"
or the "grey Box" abstraction representation). This abstraction is useful for separated compiling.
- Sequential clustering: it performs the following partitioning (called input train). Two nodes are in the same set if and
only if they depends on the same subset of inputs signals of the graph. The graph is modified. The nodes are clustered into
sub-graphs. The internal representation must be in bDC+ sub-format.
- Sequentializing (sbDC+): it performs the inter-format bDC+ (a tree of boolean clocks) to sbDC+ («sequentialized boolean
dc+») translation. The internal representation must be in bDC+ sub-format. The nodes of the internal representation
are ordered. The assert nodes are visible for code generation (code will be generated for verifying assumptions at run time).
- Flattening (STS): it performs the inter-format bDC+ (a tree of boolean clocks) to STS (a tree of boolean clocks reduces to one level)
translation. The internal representation must be in bDC+ sub-format.
Generators
There are 12 kinds of generators:
- Signal Textual (SIG): it translates the internal representation of the specification into a textual Signal file (.sig file).
- Signal Textual (LIS): it translates the internal representation of the specification into a textual Signal file (.sig file),
after the graph creation. The errors will be written on the file.
- Signal Textual (TRA): it translates the internal representation of the specification into a textual Signal file (.sig file),
after the clock calculus phase.
- Signal Model (Sme): it translates the internal representation of the specification into a XMI Model Signal file (.sme file).
This model file is conformed to the SME meta-model.
- Signal Abstraction: it translates the abstraction of the internal representation into a textual Signal file (.sig file).
- Sigali: it translates the internal representation of the specification into a textual Sigali file (.z3z file). This file is then
used by Sigali to prove dynamical properties.
- C ANSI: it translates the internal representation of the specification into a textual C ANSI files (.c and .h files). These files
are used to simulate the Signal specification. It is applied to a graph which must be a sbDC+ one. The graph is with or without
clusters.
- C++: it translates the internal representation of the specification into a textual C++ files (.cpp and .h files). These files
are used to simulate the Signal specification. It is applied to a graph which must be a sbDC+ one. The graph is with or without
clusters.
- Java: it translates the internal representation of the specification into a textual Java files (.java files). These files are
used to simulate the Signal specification. It is applied to a graph which must be a sbDC+ one. The graph is with or without clusters.
- Profiling: it produces the morphism of the internal representation according to the definitions assigned of the Signal operators
given in the "ht" table into a textual Signal file (.sig file).
- Lustre: it translates the internal representation of the specification into a textual Lustre file (.lus file).
- Syndex: it translates the internal representation of the specification into a textual SynDEx file (.sdx file) for code
distribution.
Reflexive editor
The reflexive editor has been automatically generated from the compilation scenario meta-model. To create a new compilation scenario file (.ssc), right-click on your project and select New->Other... and then select the following model: Polychrony->SME Compilation Model.
However, there are some constraints to create a compilation scenario, because some functionalities/generators can only be applied after others, so an interactive view (described in next part) has been created to help user to create such scenario.
SME Scenario View
The SME Scenario View (see following picture) constitutes a way to describe a compilation scenario with some assistance. Each functionality and generator is represented by a button and, according to the functionality or generator you activate, others become available or are disabled. Since version 0.5.0, a check box to enable/disable the display of all warnings has been added.
To access to this view, select Window-> Show View-> Other..., and then select Polychrony->SME Scenario.